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UltraZed-EV SOM memory

dougnj

I'm migrating from the PicoZed SOM to the UltraZed-EV SOM.

 

In Vivado, I'm trying to configure the DDR for the Zynq UltraScale+ MPSoC. According to the "UltraZed-EV SOM Hardware User Guide" (LIT# UG-AES-ZU7EV-SOM-G-V1.2), the memory is: MT40A512M16JY-083E IT:B. There is no preset for this part in Vivado. After some quick research, it appears this part is obsolete. If this is true, I'm hesitant to continuing to use this SOM. My project must last for years in the future. Can anyone confirm this is the part used on the SOM and whether it is obsolete?

 

Also, if this is correct, can anyone share the settings for Vivado for this part?

 

Thanks.

  • 0

    UltraZed-EV has a long life ahead of it, likely 7+ years. I know the team was qualifying a new memory. I can find out and get back with you. However, we will continue to operate the Avnet designs using the settings from the original memory since that is how the board was validated. The new Micron memory is backwards compatible with the old one.

     

    For the settings, you should be using the Avnet board definition, which you can get from the Avnet github or the Xilinx BoardStore inside Vivado. I can give you more guidance on that if you need it.

     

    Bryan

  • 0 in reply to bhfletcher

    Thanks, Bryan.

     

    As for the files, I downloaded Avnet/bdf/ultrazed_7ez_cc version 1.5 from github. I assume that's the correct one?

     

    How do I use xml files? I've only used TCL previously.

  • 0 in reply to dougnj

    If you are downloading from Avnet GitHub, then take a look at this blog

    How to Leverage Board Presets to Accelerate Your Vivado Design

     

    If you want to use the Xilinx BoardStore, then read here

    Xilinx BoardStore to Automate Vivado Board Definitions for Avnet Boards

     

    I looked at the latest Bill of Materials for UltraZed-EV, and the memory currently being used is Micron MT40A512M16LY-062E IT:E. Not only is it in Production, but as part of Micron's Product Longevity Program, it will be around for at least 10 years from the start date in 2020.

    https://www.micron.com/products/dram/ddr4-sdram/part-catalog/mt40a512m16ly-062e-it

     

    Bryan

     

  • 0 in reply to bhfletcher

    Bryan,

     

    Thanks for your help.

     

    So, I downloaded the files into my local directory and issued the following commands in Vivado:

    TCL>> set_param board.repoPaths {<PATH>}

    TCL>> create_project project_1 . -part xczu7ev-fbvb900-1-i

    TCL>> set_property board_part avnet.com:ultrazed_7ev_cc:part0:1.5 [current_project]

     

    Then, I do a "Create Block Design" and add the zynq_ultra_ps_e_0 IP and Re-customize it. I look at the DDR Configuration and it seems to be set to the default parameters, i.e. 2BG part, 800 MHz Device Freq, DDR4 1660J Speed Bin, etc. Shouldn't this be set correctly for the MT40A512M16JY-083E IT:B memory? I thought setting the board_part would configure all these parameters as well as all the others.

     

    dougnj

  • 0 in reply to dougnj

    The UltraZed-EV is using MT40A512M16LY-062E IT:E. This is what is listed in the latest BOM posted online, and the UG is out-of-date. There are 4 of these in parallel, which provides a 512M x 64bit interface, totaling 4GB.

     

    I didn't create the board definition for UltraZed-EV. The settings have to match the capabilities of the Memory device as well as the Xilinx device. In many cases, the memory is capable of much faster speeds than the Xilinx device, in which case the parameters are scaled back to match what the Xilinx device can do. The -062E is a DDR4-3200, so you'd expect to be able to run the device at 1600 MHz. However, looking at the datasheet for the XCZU7EV-1FBVB900E device, the Max capability is DDR4-2400. Therefore, the controller should never be set higher than 1200 MHz, even with the -062 populated.

     

    If the specific DDR part number existed in the Vivado catalog, you could select it, and then the tools would adjust the parameters to ensure it worked with both the SoC and the DDR. However, Avnet can't control which memory devices are placed in the default Vivado catalog. I haven't checked to see if the MT40A512M16LY-062E IT:E is there or not. We can control what is in the board definition. Any custom parameters that we put into the board definition overrides a specific DDR component selection anyway.

     

    With all that said, there is certainly room for error in our board definitions. If you are seeing something that is limiting the performance of both SoC and DDR, then we can investigate more. It sounds like 2GB and 800 MHz are not correct.

     

    Bryan