I couldn't agree more with the previous post! One of the differentiating features of the Zynq 7000 is the integrated ADC (in fact 2 ADC 1Msamples/s each). You do not find them on Altera's Cyclone V! Is there any hope to be able to use them in next versions? Is there any (equivalent) substitute available ?
An XADC Header is provided in the new I/O Carrier Card. Documentation for that has recently been posted on the site. I agree that the AMS/XADC feature of Zynq sets it apart from the competing Altera solutions. What applications are you using in for - voltage monitoring, temperature monitoring, etc.?
Would it be helpful if Avnet came out with more reference designs focusing in on XADC?
Looking at the I/O Carrier Card schematics (rev D.preliminary) it appears that it has only two differential analog inputs...
In a "real life" application, for instance for motor control, up to 16 channels are used to measure phase currents, phase voltages, temperatures, etc.
The two ADCs are started simultaneously by a timer underflow and overflow. The timer has a frequency between 4 and 100kHz. This makes a sampling frequency between 8 and 200kHz. Each ADC converts 8 channel (16 in total). At the end of conversion an interrupt is generated and the conversion results are treated by software (fast loop running at 8-200kHz). The timer is usually a PWM (Pulse Width Modulation) timer. It allows the synchronisation of PWM pulses (converter command) with the A/D conversions.
A reference design showing how to instantiate the XADC (the 16 auxiliary analogue channels), to start A/D sequences from a timer underflow/overflow and to generate PWM pulses will be greatly appreciated!
Are all the 16 auxiliary analogue XADC channels accessible at the MicroZed connectors ?(not the I/O Carrier card but the MicroZed)
I use the zed board for the main I/O for robots. So having a ADC is very useful. Not sure how many you would really need to pin out on the micro, but I would say 8 would be a good number.
I'm looking at the schematics for the MicroZed (Rev C) and it looks like the dedicated analog pair from Bank 0 is on pins 97 and 99 on JX1. But it also looks like quite a few of the I/O on JX2 are dual purpose supporting analog in. I'm looking at Bank 35 on page 6 of the schematics. Any Zynq pin that has AD{number}{P or N} are part of an analog differential pair according to page 14 of: http://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf
Is this correct or am I missing something? Does this solve your problem?
Would it be helpful if Avnet came out with more reference designs focusing in on XADC?
Any Progress on this?
I am looking to use the microzed on the io_carrier with XADC and an external mux. Looking to get 32 channels running. Also 4 bit GPIO for gain control.
Any reference design help would be greatly appreciated.
I have been working through M H Kang's Zynq how-to labs, the third of which brings up the XADC, but I have bumped into a few tool usage issues on setting the I/O constraints. A simple reference design showing how to harness VP/N, VAux0, and VAux8 would be very helpful to those of us who are fighting simultaneous Vivado, Zynq, and XADC learning curves. I have been using 2014.2, but I am tempted to try 2013.4, just so I can match Mr. Kang's steps when I get stuck. I was fine until I hit the constraints thing.
