Write data in DDR3 through PL

Hi everyone,

I have developed a vhdl file that writes data inside the DDR3. I don't have the AXI BFM licence so I simulated my AXI interface with a BRAM controller that provides an AXI slave interface and it works.

Then I connect my design to AXI HP0 of the Processing system (I delete previous BRAM controller). My problem is that no data is written inside the DDR3 when I verify it by doing a memory dump with SDK.

Do anyone have idea or a reference design or a guide or a source code that works to write data burst correctly inside the DDR3 through the PL?

Thank you

Ny

0 Former Member over 9 years ago

The AXI HP interfaces operate with the PL Logic as a Master and the PS interface as the Slave interface as opposed to the way your AXI Slave BRAM controller works. If this is what you want to implement you can take a look at this Xilinx AR for an example: http://www.xilinx.com/support/answers/54274.htm

If you want to implement logic in the PL that operates as an AXI Slave, in a similar fashion to the BRAM controller, the labs for the current Avnet Zynq HW Speedway provide an example of implementing DMA transfers from a BRAM AXI Slave in the PL to the DDR memory. If you are unable to attend the Speedway in person check with your Avnet/Silica FAE for the course materials.

-Gary
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