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DDR Configuration

Former Member

I need help configuring the memory interfaces in XPS.  I'm trying to follow the Speedway tutorial.  The ZedBoard hardware user guide specifies all the calculation results for configuring the DDR timing, but the Micro Zed doesn't have the same level of details.


I was trying to recreate Zed Board calculations (I can't find a link to the worksheet for this that Xilinx provided), and I think I was successful.  I then tried to apply the calculations to the MicroZed net lengths.


It sounds like the Zed Board only had one memory chip, while the Micro Zed has 2.  I didn't know how to compensate for that either.



I can't find the  two Micron MT41K256M16HA-125:E DDR3 memory part in the tool either.


My work so far if that helps.  I combined the Net length lists for Zed Board and Micro Zed in the same spread sheet.



https://docs.google.com/spreadsheet/ccc?key=0Ao_cHWinWfHUdER5TDMyai11eC1JUk9FcFcyUkRsVXc&usp=sharing



(not publicly editable, but commenting should be allowed)

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    We learned a lot when we designed ZedBoard, and we went to a lot more effort with MicroZed in relation to the DDR3 layout. Xilinx specifies that internal package delays should be included in the trace length matching calculations. This was not done on ZedBoard. On MicroZed, we routed and matched trace lengths to be inclusive of the internal package delay on the Zynq.

     

    You also asked what you do when there are two chips. Both ZedBoard and MicroZed have two DDR3 chips, each of which is 16-bits wide. If fly-by (daisy-chain) routing is used, then you use the mid-point between the two chips.

     

    We have pre-calculated these values for you and included them in a new Preset file that is available on the MicroZed Documentation page. You will also find 3 new tutorials posted this morning that will get you started. These tutorials will walk you through the process of using Vivado 2013.2 to create a new Zynq Hardware platform (including using the Preset file to pull in the MicroZed specific settings) and then SDK to create and run applications on MicroZed.

     

    Bryan

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    We learned a lot when we designed ZedBoard, and we went to a lot more effort with MicroZed in relation to the DDR3 layout. Xilinx specifies that internal package delays should be included in the trace length matching calculations. This was not done on ZedBoard. On MicroZed, we routed and matched trace lengths to be inclusive of the internal package delay on the Zynq.

     

    You also asked what you do when there are two chips. Both ZedBoard and MicroZed have two DDR3 chips, each of which is 16-bits wide. If fly-by (daisy-chain) routing is used, then you use the mid-point between the two chips.

     

    We have pre-calculated these values for you and included them in a new Preset file that is available on the MicroZed Documentation page. You will also find 3 new tutorials posted this morning that will get you started. These tutorials will walk you through the process of using Vivado 2013.2 to create a new Zynq Hardware platform (including using the Preset file to pull in the MicroZed specific settings) and then SDK to create and run applications on MicroZed.

     

    Bryan

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