MicroZed PS + PL with vivado 2013.4 and Linux command

Hi everybody.

I'm novice with ZYNQ SoC design. I bought a MicroZed board and I ran 01_MicroZed_Zynq_Intro_2013_2_01.pdf and Micro_zed_getting_started_v1.1.pdf tutorials. Everything was good (clear and simple).

Now I would like to generate a bitstream with PS + PL under Vivado
The idea is to implement a simple R/W register (32 bits) into PL. I would like to perform read/write on this register thanks to Linux command. Thus. I will be sure that PL is well configured.

Could you help me to do that ?
Which tools do I have to use ?
How to implement the register into PL into the Vivado project
How to connect PS to this register ?
Do I need any Linux driver to accees to the register via TeraTerm?

I know I have to convert bitstream.bit into bitstream.bit.bin as explained into xilinx AR# 46913 but I don't manage to do it.

I find this tuto MicroZed_Open_Source_Linux_In_System_QSPI_Programming_14_5_01-Tutorial but It seems to me that it needs ISE whereas I use Vivado 2013.4.

thanks very much.

best regards

Guillaume

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0 Former Member over 10 years ago

Looking through the PG078 guide for it looks like AXI-4 lite mode should work as long as you make it 32 bits wide. You should be able to read and write it the same way as any other perhiperals registers using mmap() technique. Just be aware the AXI4-Lite r/w speed is quite slow compared to regular AXI4. In a C program I was seeing about 20 MB/s. In python is was much slower.

Here's an article that's a bit more complicated and using the older tools, but you should be able to glean some insight from it.
http://www.wiki.xilinx.com/Zynq-7000+AP+SoC+PL+BRAM+Integration+with+PS

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0 Former Member over 10 years ago

Looking through the PG078 guide for it looks like AXI-4 lite mode should work as long as you make it 32 bits wide. You should be able to read and write it the same way as any other perhiperals registers using mmap() technique. Just be aware the AXI4-Lite r/w speed is quite slow compared to regular AXI4. In a C program I was seeing about 20 MB/s. In python is was much slower.

Here's an article that's a bit more complicated and using the older tools, but you should be able to glean some insight from it.
http://www.wiki.xilinx.com/Zynq-7000+AP+SoC+PL+BRAM+Integration+with+PS

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