MicroZed PS + PL with vivado 2013.4 and Linux command

I am not familiar with the tutorials you are referring to. I think perhaps you are mixing the ZedBoard and the MicroZed board. Could you clarify which board you want to work with and post links to the tutorials you have used.

-Gary

Hi Gary.

The board with which I work is MicroZed http://www.zedboard.org/product/microzed (without carrier board)

I downloaded microzed tutorials at
http://www.zedboard.org/documentation/1519.

The first tutorial (tuto 1) is MicroZed_GettingStarted_v1.1.pdf (procedure to run a simple Linux design to show a Linux application running on the ARMu00AE dual-core Cortexu2122-A9 MPCoreu2122 Processing System (PS))

The second tuto (tuto 2) I used is 01_MicroZed_Zynq_Intro_2013_2_01 at http://zedboard.org/content/vivado-20132-version-0

Everything was all right but now I would like to implement a R/W register in PL, create a bitstream.bit, download the bitstream on ZYNQ and then used Linux as I did with tuto 1 to access to this register.

Here's a brief description of the process.  It took me a while to get through this and get it working.  You'll have to figure out the steps inbetween, but here's the main steps as well as I was able to figure it out.  Somebody else might have a better way of doing this.

1) Under Vivado use the /Tools/Create and Package IP option to build an AXI4-Lite peripheral.  Add it to your block design where the processing system is. and make sure to set the address range.  You'll also likely need to add axi_interconnect and axi_protocol_converter (if routing the interface outside the block diagram).  The protocol converter is usuful if you want to route the AXI signal outside your block diagram and connect the AXI-lite bus to your IP in a regular VHDL file that has an AXI-Lite interface. 
I ended up extracting the axi4-lite exmaples vhdl file which holds the registers and then added then put my own logic into that file.  That file added to the sources and then connected in the toplevel VHDL file where the processor block diagram was also instantiated, but for simple r/w registers you can keep it all in the IP core you created.  Only downside is you have to switch to the IP core and close your project. Edit the IP core, and then reopen your project again.

2) Export the design into XSDK.  You should see the new peripheral there with its address range shown.

3) For Linux you'll need to add the new peripheral to the device tree source file and recompile it into a binary blob.

The entry will look something like this and go under the axi_interconnect: AMBA@0 section.  Your addresses and names (M00_AXI_DAQ) will be different.  So might your address width depending on how you built the core.  Again, this goes in the .dts file which you then use dtc to compile into a .dtb file and you put that on your flash. 
tt
M00_AXI_DAQ: M00_AXI_DAQ@43c10000 {
tttcompatible = "xlnx,M00_AXI_DAQ-1.0";
tttreg = <0x43c10000 0x1000>;
tttxlnx,s00-axi-addr-width = <0xC>;
tttxlnx,s00-axi-data-width = <0x20>;
tt} ;

4) You can then use mmap to map the peripheral I/O addresses into user space memory.  mmap will give you a ptr to which you can r/w data to.  You'll have to run your application as root.
I was able to get about 20 MB/s reading and writng to 32 bit registers.  Not great perormance, but it worked.

You can find more info. on the memory mapped I/O here:
http://fpgacpu.wordpress.com/2013/05/28/how-to-design-and-access-a-memory-mapped-device-part-one/

Easietst way to program the FPGA part of the zynq you is to take your myfpga.bit and convert it to a bin as explained in Xilinx AR#46913 using promgen. Promgen doesn't seem to come with the Vivado installation for some reason so you'll have to grab it from ISE 14.7 or older.

Once you have the myfpga.bin file ftp or scp it onto Linux running on the Zynq.  Once there to program all you have to do is:
cat myfpga.bin >/dev/xdevcfg
as the root user.

If you want it to load automatically you can put it on the microsd card in the first fat32 partion as system.bit.bin.  You can also package it into the FSBL using a Xilinx tool in the XSDK.

I really wish they had a good tutorial on how to do this.  I burned up a lot of time figuring it out.  Most of the tutorials use the older ISE tool flow Planahead, XPS.  I am waiting for some better tutorials on how to use Vivado with your own HDL files and the Zynq processor, but they haven't come out yet.

Best of Luck,

J

@ jbattles.
Many thanks !!! As I see, i'm not alone with difficulties to implement a simple PL architecture into ZYNQ vith vivado.

I knew Prompgen command is unavailable under Vivado (obvious).

I'm following your procedure step by step.
First, is it possible to use axi_bram_ctrl configurate AXI4-lite  ?

here's tcl console message
set_property -dict [list CONFIG.PROTOCOL {AXI4LITE}] [get_bd_cells axi_bram_ctrl_0]
INFO: [xilinx.com:ip:axi_bram_ctrl:3.0-99] design_1_axi_bram_ctrl_0_0: value of PARAM_VALUE.PROTOCOL = AXI4LITE
INFO: [xilinx.com:ip:axi_bram_ctrl:3.0-99] design_1_axi_bram_ctrl_0_0: value of PARAM_VALUE.SUPPORTS_NARROW_BURST = 0
INFO: [xilinx.com:ip:axi_bram_ctrl:3.0-565] design_1_axi_bram_ctrl_0_0: Protocol value = AXI4LITE
INFO: [xilinx.com:ip:axi_bram_ctrl:3.0-99] design_1_axi_bram_ctrl_0_0: value of PARAM_VALUE.DATA_WIDTH = 32
INFO: [xilinx.com:ip:axi_bram_ctrl:3.0-99] design_1_axi_bram_ctrl_0_0: value of PARAM_VALUE.MEM_DEPTH = 1024
INFO: [xilinx.com:ip:axi_bram_ctrl:3.0-99] design_1_axi_bram_ctrl_0_0: value of PARAM_VALUE.USE_ECC = 0
INFO: [xilinx.com:ip:axi_bram_ctrl:3.0-99] design_1_axi_bram_ctrl_0_0: value of PARAM_VALUE.ECC_ONOFF_RESET_VALUE = 0
INFO: [xilinx.com:ip:axi_bram_ctrl:3.0-99] design_1_axi_bram_ctrl_0_0: value of PARAM_VALUE.FAULT_INJECT = 0
INFO: [xilinx.com:ip:axi_bram_ctrl:3.0-99] design_1_axi_bram_ctrl_0_0: value of PARAM_VALUE.ECC_TYPE = 0

Looking through the PG078 guide for it looks like AXI-4 lite mode should work as long as you make it 32 bits wide.  You should be able to read and write it the same way as any other perhiperals registers using mmap() technique.  Just be aware the AXI4-Lite r/w speed is quite slow compared to regular AXI4.  In a C program I was seeing about 20 MB/s.  In python is was much slower.

Here's an article that's a bit more complicated and using the older tools, but you should be able to glean some insight from it.
http://www.wiki.xilinx.com/Zynq-7000+AP+SoC+PL+BRAM+Integration+with+PS

J