Vivado 2014.4 MicroZed incompatible board definition file

I was able to replicate your errors with the project file you posted on the Xilinx community forum with the MicroZed using Vivado 2014.4. However, when I target the Xilinx ZC702 board with a similar design I get the same errors, so it appears to be an issue with Vivado 2014.4 and not the MicroZed Board Definition files.

We will check with Xilinx and see if there is some addition that needs to be made to the board definition files to accommodate Vivado 2014.4 but, since the Xilinx evaluation board fails in the same manner, that may not be the issue.

-Gary

Thank You Gary,

I really appreciate your help. The information below might help (you or Xilinx) sort things out.

I (re,re,re) started from a blank project, without using any board du00E9finitions file for the MicroZed.

I declared the same Zynq part and memory part as found in Vivado 2014.2 Summary Report (Zynq processor block). I used the same parameters, etc.

I did a minimalistic project (only the processor).

First annomaly I see the UNUSED pins of the Bank0 as default(LVCMOS18). I declared the BANK0 as LVCMOS33. It is impossible to change this property to LVCMOS33.

I tried to run a Hello World application (creating Platform, bsp, hello world application).
It does not work.

I can run step by step but I receive no "Hello World" message neither on Terra Term nor on the SDK console. I tried it multiple times.

So the problem seems much more deep than the Microzed du00E9finitions.

I will shortly post the archive in Xilinx community forums.

Best Regards,
Cristian

For those who might want to reproduce the problem  please find below the post that contained a simple project (MicroZed 7020).

http://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/Vivado-2014-4-Bug-when-starting-from-scratch/td-p/551083

Regards,

Well, I am un-certain to here this post that the bdf of microzed is not compatible with 2014.4.

I just upgrade to 2014.4 webpack, I am watching this post before avnet/xilinx made any update to the bdf file.

There is not a problem with the current (2014.2) MicroZed board definition files and Vivado 2014.4. We have confirmed with Xilinx that board definition files generated for Vivado 2014.2 should be compatible with Vivado 2014.4 as well.

The problem Nitron had also manifested itself with a Xilinx ZC702 evaluation board in the same way. I believe it is related to the way Vivado 2014.4 handles some of the Zynq Bank 0 I/O. It looks like you must explicitly constraint some of the Bank 0 I/O (the Vp-Vn signals in Nitron's case) where you did not have to in Vivado 2014.2. If I add a constraints file with the following lines to the project Nitron posted on the Xilinx forums linked above it corrects the issue:

# Set the bank voltage for bank 0.

set_property IOSTANDARD LVCMOS33 [get_ports -filter { IOBANK == 0 } ]

set_property PACKAGE_PIN K9 [get_ports {Vp_Vn_v_p}]

set_property PACKAGE_PIN L10 [get_ports {Vp_Vn_v_n}]

So, not an issue with the MicroZed board definition files. You should be able to use them with Vivado 2014.4

Regards,

-Gary

Thank You so much for your support!

I tried your suggestions in the following way:
   I created an additional constraints file (not the target one) in which I added the constraints you suggested.
   Basically I'm working with two file constraints, one (the target) is generated by Vivado and the other one by me.
    After setting the bank voltage for Bank 0 I got rid of the MIO warnings. YES!
    However when inspecting the I/O Planning I/O Ports tab I saw that all the MIO including the ones in bank 1 are forced an LVCMOS33. That's a little bit annoying since I defined these pins as LVCMOS18 in Vivado. Is this LVCMOS33 safe with Bank 1 and MicroZed?
    My additionnal constraints file looks like this:

set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
# Set the bank voltage for bank 0.
set_property IOSTANDARD LVCMOS33 [get_ports -filter { IOBANK == 0 } ]

The last two lines you sugested (VN/VP constraints) generate two critical warnings so I had to eliminate them. However I was able to make external Vp/Vn and Vivado generated the right pins allocation (generating automatically an Vcco=3.3V).

The only warning that remains is :
ADEF #1 Warning Cell MZ_HW_i/xadc_wiz_0/U0/AXI_XADC_CORE_I/XADC_INST has the SIM_DEVICE attribute set to ZYNQ, but the current architecture is ZYNQ. The SIM_DEVICE attribute must match the loaded architecture. To correct this issue set the SIM_DEVICE attribute for this cell to 7SERIES.

I suppose it is safe to ignore this warning even if MicroZed isn't equipped with 7SERIES.

Anyway it is very usefull to konw that you recommend using the Vivado 2014.2 definition for Vivado 2014.4

Best Regards and Thank You,
Cristian
 
  
Best Regards,
Cristian 

Hello Cristian,

LVCMOS33 is NOT safe with Bank 1 on the MicroZed. The Bank 1 I/O should not be set to 3.3V. I looked at the I/O report and I see the same thing you do, even though the MIO settings in the processing system in the block design clearly have them set to 1.8V. At this point I don't know if Vivado is setting it incorrectly or if the I/O report is wrong. Again I duplicated the behaviour with a ZC702 board desgin. I will submit a case to Xilinx to find out.

The Zynq device is a 7SERIES device. I think these warnings are benign.

I will post an update when I have a response.

-Gary

The Bank 1 (actually Bank 501) I/O error was caused by my incorrect constraint. As there is no Bank 0 (really bank 500) my incorrect constraint caused Vivado to set all of the I/O to LVCMOS33. If I correct my constraint file to be:

set_property PACKAGE_PIN K9 [get_ports {Vp_Vn_v_p}]
set_property PACKAGE_PIN L10 [get_ports {Vp_Vn_v_n}]

set_property  IOSTANDARD LVCMOS33 [get_ports {Vp_Vn_v_p}]
set_property IOSTANDARD LVCMOS33 [get_ports {Vp_Vn_v_n}]

then I am able to generate a bitstream without errors and with the correct I/O standards. Sorry for the confusion.

I am still working to find out why the original 'no constraints' version works in Vivado 2014.2 and fails in Vivado 2014.4

-Gary

Got an answer from Xilinx. The new errors in Vivado 2014.4 are caused by the tool inferring IO buffers on the Vp_Vn_v_n, Vp_Vn_v_p ports from the XADC. This will be resolved in a future release of Vivado by adding the pins to a list exempting them from iobuffer insertion.

In the meantime the work around is to add I/O constraints, as discussed above, or possibly manually removing the inserted IO buffers.

-Gary

Gary,

Thank you for the information.

Concerning the constraints:

  set_property PACKAGE_PIN K9 [get_ports {Vp_Vn_v_p}]
set_property PACKAGE_PIN L10 [get_ports {Vp_Vn_v_n}]
set_property IOSTANDARD LVCMOS33 [get_ports {Vp_Vn_v_p}]
set_property IOSTANDARD LVCMOS33 [get_ports {Vp_Vn_v_n}]

Unfortunately I could not reproduce your results.

At this stage I have to say that my application uses also 8 Aux XADC inputs in addition to Vp/Vn. Just using 8 XADC inputs for tempu00E9ratures measurement !
Constraining these inputs is apparently not compatible with the constraints for Vp/Vn.
I get 4 critical warnings saiyng:

[Common 17-55] 'set_property' expects at least one object. [C:/ZynqProjects/2014_4/MZ_HW/MZ_HW.srcs/constrs_1/new/MZ_HW_App.xdc:3]
Resolution: If [get_<value>] was used to populate the object, check to make sure this comm     and returns at least one valid object.

The 4 critical warnings correspond to the 4 constraints lines above.

So it's preferable to constraint the Vaux inputs (in I/O planning select Vauxn0 to B20) and to avoid constraining Vp/VN.

Of course I couldn't get rid of the initial warning:

#1 Warning An IO Bus FIXED_IO_mio[53:0] with more than one IO standard is found. Components associated with this bus are:  FIXED_IO_mio[53] of IOStandard LVCMOS18; .......

I guess I'll have to live with this until a "future" version of Vivado.

I am really sorry to see this since I acknowledge You made a lot of efforts to solve the issue.
  I'm just giving my input for you and other users that might have the same problem.

Best Regards,
Cristian