Hi all,
I was directed towards this forum in order to signal that board definition files (from Vivado 2014.2) are incompatible with the Vivado 2014.4.
I encountered this incompatibility when working with a MicroZed 7020.
The incompatibilities appear at least when instantiating the XADC. A warning appears also about the MIO pins.
In order to help reproduce the problem a detailed description of the issue can be found at:
http://forums.xilinx.com/t5/Zynq-All-Programmable-SoC/Vivado-2014-4-error-Unable-to-place-all-the-instance-of-site/td-p/549590
I have posted also a simplified project built from scratch in Vivado 2014.4 in order to allow reproducing the problem. The MicroZed definition files where imported from Vivado 2014.2.
Note:
With the help of Xilinx (John McGrath) I managed to generate the bitstream by doing the following
-I deleted VP/VN external connection
-I declared Aux1-7 as ADC inputs with "Make External" command for each polarity P and N.
-In I/O planning tab I declared the P and N polarities as IOSTANDARD LVCMOS18
-For Vauxn0 ONLY I selected the site B20 (I/O planning tab). Then AUTOMATICALLY all the pins were positioned by VIVADO!
The bistream is generated succesfully but with a LOT of critical warnings of type:
[Common 17-55] 'set_property' expects at least one object. ["C:/ZynqProjects/2014_4/MZ_CMD/MZ_CMD.srcs/constrs_1/new/MZ_CMD_BD_wrapper.xdc":19]
This warning is generated for the most of the lines in the .xdc file (automatically generated by Vivado)
When inspecting the .xdc file it appears that Vivado 2014.4 forces the IOSTANDARD of some pins to LVCMOS33 instead of LVCMOS18.
I tried to put everywhere LVCMOS33 like in all the previous applications, blogs, tuto, etc.
In this case you can see in the .xdc file that Vauxn0 is forced by Vivado at LVCMOS18 ! I could not get rid of warnings... so I STARTED ONCE AGAIN FROM ABSOLUTE SCRATCH.
I opened simultaneously Vivado 2014.2 and Vivado 2014.4 and created a new project selecting the Zynq component, manually transferring the memory data parameters (training + etc.) and the allocation of the pins. I followed Lab2 (Speedway).
Finally I get rid of most of the warnings.
However some warnings subsist in the .drc report:
-----------------
ADEF-911#1 Warning
SIM_DEVICE_arch_mismatch
Cell MZ_HW_CMD_i/xadc_wiz_0/U0/AXI_XADC_CORE_I/XADC_INST has the SIM_DEVICE attribute set to ZYNQ, but the current architecture is ZYNQ. The SIM_DEVICE attribute must match the loaded architecture. To correct this issue set the SIM_DEVICE attribute for this cell to 7SERIES.
Related violations: <none>
CFGBVS-1#1 Warning
Missing CFGBVS and CONFIG_VOLTAGE Design Properties
Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
set_property CFGBVS value1 [current_design]
#where value1 is either VCCO or GND
set_property CONFIG_VOLTAGE value2 [current_design]
#where value2 is the voltage provided to configuration bank 0
Refer to the device configuration user guide for more information.
Related violations: <none>
PLIO-7#1 Warning
Placement Constraints Check for IO constraints
An IO Bus FIXED_IO_mio[53:0] with more than one IO standard is found. Components associated with this bus are: FIXED_IO_mio[53] of IOStandard LVCMOS18; FIXED_IO_mio[52] of IOStandard LVCMOS18; FIXED_IO_mio[51] of IOStandard LVCMOS18; FIXED_IO_mio[50] of IOStandard LVCMOS18; FIXED_IO_mio[49] of IOStandard LVCMOS18; FIXED_IO_mio[48] of IOStandard LVCMOS18; FIXED_IO_mio[47] of IOStandard LVCMOS18; FIXED_IO_mio[46] of IOStandard LVCMOS18; FIXED_IO_mio[45] of IOStandard LVCMOS18; FIXED_IO_mio[44] of IOStandard LVCMOS18; FIXED_IO_mio[43] of IOStandard LVCMOS18; FIXED_IO_mio[42] of IOStandard LVCMOS18; FIXED_IO_mio[41] of IOStandard LVCMOS18; FIXED_IO_mio[40] of IOStandard LVCMOS18; FIXED_IO_mio[39] of IOStandard LVCMOS18; FIXED_IO_mio[38] of IOStandard LVCMOS18; FIXED_IO_mio[37] of IOStandard LVCMOS18; FIXED_IO_mio[36] of IOStandard LVCMOS18; FIXED_IO_mio[35] of IOStandard LVCMOS18; FIXED_IO_mio[34] of IOStandard LVCMOS18; FIXED_IO_mio[33] of IOStandard LVCMOS18; FIXED_IO_mio[32] of IOStandard LVCMOS18; FIXED_IO_mio[31] of IOStandard LVCMOS18; FIXED_IO_mio[30] of IOStandard LVCMOS18; FIXED_IO_mio[29] of IOStandard LVCMOS18; FIXED_IO_mio[28] of IOStandard LVCMOS18; FIXED_IO_mio[27] of IOStandard LVCMOS18; FIXED_IO_mio[26] of IOStandard LVCMOS18; FIXED_IO_mio[25] of IOStandard LVCMOS18; FIXED_IO_mio[24] of IOStandard LVCMOS18; FIXED_IO_mio[23] of IOStandard LVCMOS18; FIXED_IO_mio[22] of IOStandard LVCMOS18; FIXED_IO_mio[21] of IOStandard LVCMOS18; FIXED_IO_mio[20] of IOStandard LVCMOS18; FIXED_IO_mio[19] of IOStandard LVCMOS18; FIXED_IO_mio[18] of IOStandard LVCMOS18; FIXED_IO_mio[17] of IOStandard LVCMOS18; FIXED_IO_mio[16] of IOStandard LVCMOS18; FIXED_IO_mio[15] of IOStandard LVCMOS33; FIXED_IO_mio[14] of IOStandard LVCMOS33; FIXED_IO_mio[13] of IOStandard LVCMOS18; FIXED_IO_mio[12] of IOStandard LVCMOS18; FIXED_IO_mio[11] of IOStandard LVCMOS33; FIXED_IO_mio[10] of IOStandard LVCMOS33; FIXED_IO_mio[9] of IOStandard LVCMOS18; FIXED_IO_mio[8] of IOStandard LVCMOS18; FIXED_IO_mio[7] of IOStandard LVCMOS18; FIXED_IO_mio[6] of IOStandard LVCMOS18; FIXED_IO_mio[5] of IOStandard LVCMOS18; FIXED_IO_mio[4] of IOStandard LVCMOS18; FIXED_IO_mio[3] of IOStandard LVCMOS18; FIXED_IO_mio[2] of IOStandard LVCMOS18; FIXED_IO_mio[1] of IOStandard LVCMOS18; FIXED_IO_mio[0] of IOStandard LVCMOS18;
Related violations: <none>
I do not know how to get rid of these last warnings...
Is it possible to have some updated board definition files for Vivado 2014.4 ?
I find really dissapointing the incompatibilities between successive versions of Vivado. How can on maintain applications for years if the Tools are changing every 3-6 months ?
Regards,
