Building MicroZed hardware in Vivado problem

You selected the Zynq7 Processing System BFM (Bus Functional Model) when you added your initial IP to the block design rather than the Zynq7 Processing System IP.

The Bus Functional Model does require an additional license.

-Gary

I rebuilt to make sure- selecting the ZYNQ7 Processing System (second choice from the bottom of the list) results in the aforementioned warnings. Was there a change between 2013.2 and 2013.4 that would cause that? There is a small difference between the tutorial and what I see; in the tutorial, the block diagram on page 10 is labled "processing_system7_1", whereas the one on my computer is labled "processing_system7_0". I don't know if this makes a difference or if there are other changes as well.

There are some differences between 2013.2 and 2013.4, such as the fact that the MicroZed board is included as a preset in 2013.4 and you do not need to load the board awareness files. You should use the built in MicroZed presets for 2013.4. The different appended _0 or _1 to the IP should have no real impact except that you might need to adjust the parameter names to match in any software written with one of the versions in mind.

I am not sure why you are having an issue if you are really selecting Zynq7 Processing System, I just tried it and it works fine in Vivado 2013.4. I would suggest starting over with a new project.

-Gary

with two different installations are producing the same warnings listed in the OP. I'm going to try 2013.3 to see if it makes a difference.

You might want to check the MD5 sum of the file you downloaded to install Vivado 2013.4. I have seen cases where odd behavior such as this has been traced to corrupted Vivado installation files. I have built several MicroZed based designs using Vivado 2013.4 without running into the issue you describe.

-Gary

I just downloaded and installed 2013.3 and got the exact same warnings- is there something wrong with my Vivado license? MD5 checked out with both versions - this is getting frustrating.

Here is the output for building in 2013.3

create_project MZ_Basic_System C:/Xilinx/Projects/MZ_Basic_System -part xc7z010clg400-1
create_project: Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 693.590 ; gain = 6.984
set_property board em.avnet.com:zynq:microzed:e [current_project]
INFO: [IP_Flow 19-2313] Loaded Vivado repository 'C:/Xilinx/Vivado/2013.3/data/ip'.
create_bd_design "System"
Wrote  : <C:/Xilinx/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/System.bd>
create_bd_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:05 . Memory (MB): peak = 694.309 ; gain = 0.719
startgroup
create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.3 processing_system7_0
create_bd_cell: Time (s): cpu = 00:00:03 ; elapsed = 00:00:08 . Memory (MB): peak = 715.793 ; gain = 12.348
endgroup
source C:/Xilinx/MicroZed_PS_properties_v02.tcl

# set_property -dict [ list
# tCONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V}
.......

apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" apply_board_preset "1" }  [get_bd_cells processing_system7_0]
apply_bd_automation: Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 736.844 ; gain = 17.828
validate_bd_design
success
generate_target all [get_files  C:/Xilinx/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/System.bd]
Verilog Output written to : System.v
Verilog Output written to : System_wrapper.v
Wrote  : <C:/Xilinx/Projects/MZ_Basic_System/MZ_Basic_System.srcs/sources_1/bd/System/System.bd>
Delivering 'Verilog Instantiation Template' file for IP 'System_processing_system7_0_0'.
Delivering 'Vivado Synthesis' files for IP 'System_processing_system7_0_0'.
Delivering 'Vivado Simulation' files for IP 'System_processing_system7_0_0'.
WARNING: [IP_Flow 19-2987] IP 'System_processing_system7_0_0' with unlicensed IP definition 'xilinx.com:ip:processing_system7:5.3' depends on licensed subcore IP definition 'xilinx.com:ip:processing_system7_bfm:2.0'. Please update your IP definition with license information.
WARNING: [xilinx.com:ip:processing_system7:5.3-1] System_processing_system7_0_0: The Zynq BFM requires an AXI BFM license to run. Please ensure that you have purchased and setup the AXI BFM license prior to running simulation with this block. Please contact your Xilinx sales office for more information on purchasing this license
Delivering 'Miscellaneous' files for IP 'System_processing_system7_0_0'.
INFO: [BD 41-1029] Generation completed for the IP Integrator block /processing_system7_0 .
generate_target: Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 818.246 ; gain = 0.000

Once you have gone through a process many times it is easy to miss the steps you really take and do not take. I went back and traced through the tutorial line by line with Vivado 2013.4. You do not need to perform steps 5-8 on page 10 as that is now handled by the MicroZed preset. Step 17, Generate Output Products, on page 15 is now done automatically as well, but I did go ahead and perform the step and that is where I did get the warnings you are seeing. I don't know why it generates a 'BFM' warning at this step but it can be safely ignored. I was able to complete the tutorial from here.

-Gary

Hello,

I have the same warning in Vivado 2014.2. The warning appears when clicking on "Generate Output Products".

Starting with a project from scratch does not help.

Seems that even in the version 2014.2 this problem has not been sorted out.

You can still safely ignore the 'BFM' warning if you do not intend to use the Bus Functional Model for simulation.

-Gary