JX1/JX2 Track Impedance

One of the selling points of the MicroZed is the high quality high frequency connectors JX2 and JX2, since unlike many boards they allow many high frequency signals to be connected to the Zynq.

I'd like to ensure high speed signal integrity for signals going from a carrier board through JX 1 and JX2 to the Zynq. The key parts are the Zynq input pin standard (LVDS etc) and the track impedance on the carrier board (my responsibility) and the track impedance for the 2" tracks on the MicroZed board. At GHz bit rates, a 2" track is electrically long, and simulations show the difference between 40ohms and 80ohms is significant.

Now the DDR tracks are 40ohms, but what's the "typical" impedance of the tracks from the JX1/2 connectors? N.B. I'm neither after specifications nor guarantees, but I would like an indication of likely impedance.

If that isn't known, what's the track width and pre-preg thickness, and I'll make a guesstimate from that.

Thanks.

Parents

0 e14 Contributor over 12 years ago

I checked with the board designer and his reply was:

Per the UG:
100 ohm diff, 50 ohm single ended.

All signals shall be routed to meet the following requirements:

·         100 ohm differential impedance between the P/N pairs.

·         10 mil length difference between each P/N pair on each header.

·         Use 4x spacing between pairs.

·         Length-tune ALL P/N signal pairs to within 100 mils across all pairs, including the internal 7010-CLG400 package delays.

o   Length tune JX1, entire group (all connector P/N pairs) to within 100mils of each other. The zero point, or reference point, is the longest pair in the group and all lengths are referenced to this length. Length tune within each P/N pair to 10 mils of each other.

o   Length tune JX2 in the same manner are JX1.

o   Length tune Bank 13 in the same manner as JX1.

·         Power (VCCO_xx) and Ground nets should be capable of handling 0.8A.

·         The dedicated analog signals, VP_0, VN_0, DXP and DXN should be isolated as much as possible from other noisy signals.

·         If possible, the auxiliary/multi-use analog signals, IO_L*P_T1_AD*P/N_* should provide as much isolation as possible. Some of these are shared with DQ byte groups above, in these cases, the DQ routing takes precedence.

-Gary
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0 e14 Contributor over 12 years ago

I checked with the board designer and his reply was:

Per the UG:
100 ohm diff, 50 ohm single ended.

All signals shall be routed to meet the following requirements:

·         100 ohm differential impedance between the P/N pairs.

·         10 mil length difference between each P/N pair on each header.

·         Use 4x spacing between pairs.

·         Length-tune ALL P/N signal pairs to within 100 mils across all pairs, including the internal 7010-CLG400 package delays.

o   Length tune JX1, entire group (all connector P/N pairs) to within 100mils of each other. The zero point, or reference point, is the longest pair in the group and all lengths are referenced to this length. Length tune within each P/N pair to 10 mils of each other.

o   Length tune JX2 in the same manner are JX1.

o   Length tune Bank 13 in the same manner as JX1.

·         Power (VCCO_xx) and Ground nets should be capable of handling 0.8A.

·         The dedicated analog signals, VP_0, VN_0, DXP and DXN should be isolated as much as possible from other noisy signals.

·         If possible, the auxiliary/multi-use analog signals, IO_L*P_T1_AD*P/N_* should provide as much isolation as possible. Some of these are shared with DQ byte groups above, in these cases, the DQ routing takes precedence.

-Gary
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