Can any one weigh in and let me know what's wrong with my basic example below?
I've implemented a very simple tri state example. I've copied two pieces of code below which correspond to the two different oscilliscope images in the attached picture. I constrained the inout csb as it connects on the top level in my block diagram as an internal pull up. I would expect to be able to toggle the pull up using verilog code A below but the inout port stays low for some reason. It seems like it gets stuck I'm hoping that what ever is wrong here is also the problem with my SPI interface.
This is done with a 7z010 Microzed and Vivado tools 2014.1
I don't see anywhere to attach my picture , I'll look more for the option after posting
Thanks so much,
Sam
///////////////////////////////////////////////////////////
//verilog code A
module tri_stated(
inout csb,
input clk,
input reset
);
reg oreg;
assign csb = oreg;
reg data;
reg [15:0] count;
wire oen;
assign oen = count[3];
initial oreg = 1'bz;
always @(posedge clk)
if(reset)begin
count <= 16'd0;
end else
count <= count + 1'b1;
always @(oen or oreg)
if (oen == 1'b1)
oreg = 1'd0;
else if(oen == 1'b0)
oreg = 1'bz;
endmodule
///////////////////////////////////////////////////////////
//Verilog code B
module tri_stated(
inout csb,
input clk,
input reset
);
reg oreg;
assign csb = oreg;
reg data;
reg [15:0] count;
wire oen;
assign oen = count[3];
initial oreg = 1'bz;
always @(posedge clk)
if(reset)begin
count <= 16'd0;
end else
count <= count + 1'b1;
always @(oen or oreg)
if (oen == 1'b1)
oreg = 1'bz;
else if(oen == 1'b0)
oreg = 1'bz;
endmodule
