Creating a MIG Block for microZed-020

Question

Another toss-up of this topic list or the Xilinx Tools list...

Has anyone created a MIG block to split off the 1G DDR3 from the PS for use by PL designs?

This is my first time running the MIG and I have questions like:

* Ok, we set the Controller Options memory type which is x16, but then there's a pull-down box asking for 8/16/32/64bit Data Width.

* AXI Parameters: Data Width: 32 or 64? Arbitration Scheme?

* Memory Options: Input Clock Period defaults to 11250pS. Should this be changed? What about any additional clocks? (and then the options below?)

* FPGA Options: ANything needing changing here? (I already have an XADC)

Extended FPGA Options: uZed020 says 40ohms?

Pin Selection: (ugh. Anyone got a UCF file they'd share?)

Etc...etc...

Thanks,

-Ben

EDIT: now that I'm closely reading this.. I'm wondering if the MIG is only useful for memory attached to PL available pins (i.e. the MIG won't work for PS controller attached memory?)

bkamen · Accepted Answer

Hey Josh -- Thanks..

I did check that out -- but actually found this a little more helpful with the initial setup (that part isn't too hard... but validation is a good thing..)

http://www.fpgadeveloper.com/2014/08/using-the-axi-dma-in-vivado.html

And also:

https://www.xilinx.com/support/answers/57550.html

And finally: for LInux (although a little old)

https://forums.xilinx.com/t5/Embedded-Linux/AXI-DMA-with-Zynq-Running-Linux/m-p/522755/highlight/true#M10649

Hopefully this is helpful for others...

-Ben