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SPI From Chosen Pins to Ethernet

Former Member

Hello all,

I'm having trouble getting SPI to behave as desired. Very much a noob here so, be gentle.

The ports I wish to use for SPI via LVDS are located on the breakout carrier card.

The data being sent is via SPI with an accompanying GPIO pin that determines which "side" of the data is being sent.

Once both sides of the data is received, it's then packaged and sent via UDP through the ethernet port.

Inside Vivado, I cannot choose which ports are used for the SPI.

Is this done within the SDK? I would prefer that the FPGA side of things handles the SPI and the Arm merely handles the UDP package.

Within Vivado, I have the SPI_0 activated in the ZYNQ7 Processing System. (But no inputs to the module?)

I seem to have some fundamental design flow issues wrong and I'm wondering if someone has a link to an SPI tutorial on the Zynq.

Logically, I assume I can just map the GPIOs to a custom IP that handles the SPI and output it to DRAM and handle it in C... I think.

Thanks in advance for the help. I've recently started learning FPGA development and any direction here would be greatly appreciated!

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    You can control the ports assigned to the SPI controller in Vivado. Normally SD0 in the Zynq PS (Processing System) is connected to the QSPI Flash device on the MicroZed via MIO pins 40 - 45. If you want to keep the QSPI peripheral you can either enable the Zynq PS SD1 peripheral and set it's IO to the 'EMIO' or instantiate an AXI Quad SPI controller in the PL (Programmable Logic) section.

     

    Assuming you want to use the PS SD1 controller, once you have selected EMIO IO for the device the SD1 ports will appear on the Zynq Processing System block in your Vivado design. You can 'Make External' the whole interface or expand the SD1 port and connect to the individual signals you want. You can then connect these SD controller signals to logic in the PL or directly to ZYNQ IO pins that are connected to the MicroZed MicroHeaders by creating a constraints file (.xdc file type) specifying the pins each signal is to be connected to.

     

    You will need to look at the MicroZed HW Users Guide and the Break Out Carrier Card Users Guide to determine which Zynq device IO you want to select in your constraints file. The MicroZed HW Users Guide and MicroZed Carrier Design Guide are here: http://zedboard.com/support/documentation/1519

     

    The MicroZed Break Out Carrier Card documents are here: http://zedboard.com/support/documentation/2182

     

     

    Same thing for the GPIO. You can select EMIO IO for the PS GPIO or instantiate an AXI GPIO controller.

     

    While they do not specifically address using the SD1 peripheral the general process is detailed in the Avnet Developing ZynqRegistered-7000 All Programmable SoC Hardware (Vivado 2013.3) Speedway design seminar that can be downloaded here: http://zedboard.com/support/trainings-and-videos

     

    Adam Taylor also has an excellent blog that steps you through developing Zynq Designs for the MicroZed board. The first blog entry is here:

    http://forums.xilinx.com/t5/Xcell-Daily-Blog/Bringing-up-the-Avnet-MicroZed-with-Vivado/ba-p/362901

     

    -Gary

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  • 0

    You can control the ports assigned to the SPI controller in Vivado. Normally SD0 in the Zynq PS (Processing System) is connected to the QSPI Flash device on the MicroZed via MIO pins 40 - 45. If you want to keep the QSPI peripheral you can either enable the Zynq PS SD1 peripheral and set it's IO to the 'EMIO' or instantiate an AXI Quad SPI controller in the PL (Programmable Logic) section.

     

    Assuming you want to use the PS SD1 controller, once you have selected EMIO IO for the device the SD1 ports will appear on the Zynq Processing System block in your Vivado design. You can 'Make External' the whole interface or expand the SD1 port and connect to the individual signals you want. You can then connect these SD controller signals to logic in the PL or directly to ZYNQ IO pins that are connected to the MicroZed MicroHeaders by creating a constraints file (.xdc file type) specifying the pins each signal is to be connected to.

     

    You will need to look at the MicroZed HW Users Guide and the Break Out Carrier Card Users Guide to determine which Zynq device IO you want to select in your constraints file. The MicroZed HW Users Guide and MicroZed Carrier Design Guide are here: http://zedboard.com/support/documentation/1519

     

    The MicroZed Break Out Carrier Card documents are here: http://zedboard.com/support/documentation/2182

     

     

    Same thing for the GPIO. You can select EMIO IO for the PS GPIO or instantiate an AXI GPIO controller.

     

    While they do not specifically address using the SD1 peripheral the general process is detailed in the Avnet Developing ZynqRegistered-7000 All Programmable SoC Hardware (Vivado 2013.3) Speedway design seminar that can be downloaded here: http://zedboard.com/support/trainings-and-videos

     

    Adam Taylor also has an excellent blog that steps you through developing Zynq Designs for the MicroZed board. The first blog entry is here:

    http://forums.xilinx.com/t5/Xcell-Daily-Blog/Bringing-up-the-Avnet-MicroZed-with-Vivado/ba-p/362901

     

    -Gary

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