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MicroZed Vivado Design Issue

raymadigan

I am not sure what to do at this point.  I  have tried everything I can think of except a new MicroZed board.

I have a design that uses a custom AXI Lite IP.   Basically I want to allocate N registers and have N/2 be read/write and the other N/2 be read only.  The read only registers will be written to by my application. 

I have build the design and none of my changes have any effect when I run the application on my uZed.  I have commented out the entire process that writes the register to the AXI output pins.  This change has no effect on the application, it still runs as the original AXI Lite IP.

I have asked countless times in the Vivado, Design Entry, Zynq forums and nobody has an idea of how to overcome this problem.

I have a very very early uZed.  Is there any suggestions to overcome this issue.

Is there a test I can run to determine where the issue might be.

I have a very similar problem with an AXI Stream Master IP I am trying to build.

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    I made the following change to the vhdl

    t-- Implement memory mapped register select and read logic generation
    t-- Slave register read enable is asserted when valid address is available
    t-- and the slave is ready to accept the read address.
    tslv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;

    tprocess (slv_reg0, slv_reg1, slv_reg2, slv_reg3, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
    tvariable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
    tbegin
    t    -- Address decoding for reading registers
    t    loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
    t    case loc_addr is
    t      when b"00" =>
    t        reg_data_out <= (others => '0'); --slv_reg0;
    //and at the end of the same process
    t      when others =>
    t        reg_data_out  <= (others => '0');
    t    end case;
    tend process;

    The 0'th register and all registers greater then register 3 should be zero

    If I change my main to this:
        int foo = CCMLITEDEMO_mReadReg(&BaseAddress, 0);
        printf("Reg 0: %d
    r", foo);

        CCMLITEDEMO_mWriteReg(&BaseAddress, 0, 54321);
        int bar = CCMLITEDEMO_mReadReg(&BaseAddress, 0);
        printf("Reg 0: %d
    r", bar);

        CCMLITEDEMO_mWriteReg(&BaseAddress, 24 , 98765);
        bar = CCMLITEDEMO_mReadReg(&BaseAddress, 24);
        printf("Reg 6: %d
    r", bar);

    the output is:

    Hello World
    Reg 0: 1136656384
    Reg 0: 54321
    Reg 6: 98765

    Register 6 should be zero, there is no register 6 defined in the vhdl.

    All I can assume is a different VHDL is running on the board that implements all registers.

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  • 0

    I made the following change to the vhdl

    t-- Implement memory mapped register select and read logic generation
    t-- Slave register read enable is asserted when valid address is available
    t-- and the slave is ready to accept the read address.
    tslv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;

    tprocess (slv_reg0, slv_reg1, slv_reg2, slv_reg3, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
    tvariable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
    tbegin
    t    -- Address decoding for reading registers
    t    loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
    t    case loc_addr is
    t      when b"00" =>
    t        reg_data_out <= (others => '0'); --slv_reg0;
    //and at the end of the same process
    t      when others =>
    t        reg_data_out  <= (others => '0');
    t    end case;
    tend process;

    The 0'th register and all registers greater then register 3 should be zero

    If I change my main to this:
        int foo = CCMLITEDEMO_mReadReg(&BaseAddress, 0);
        printf("Reg 0: %d
    r", foo);

        CCMLITEDEMO_mWriteReg(&BaseAddress, 0, 54321);
        int bar = CCMLITEDEMO_mReadReg(&BaseAddress, 0);
        printf("Reg 0: %d
    r", bar);

        CCMLITEDEMO_mWriteReg(&BaseAddress, 24 , 98765);
        bar = CCMLITEDEMO_mReadReg(&BaseAddress, 24);
        printf("Reg 6: %d
    r", bar);

    the output is:

    Hello World
    Reg 0: 1136656384
    Reg 0: 54321
    Reg 6: 98765

    Register 6 should be zero, there is no register 6 defined in the vhdl.

    All I can assume is a different VHDL is running on the board that implements all registers.

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