I am not sure what to do at this point. I have tried everything I can think of except a new MicroZed board.
I have a design that uses a custom AXI Lite IP. Basically I want to allocate N registers and have N/2 be read/write and the other N/2 be read only. The read only registers will be written to by my application.
I have build the design and none of my changes have any effect when I run the application on my uZed. I have commented out the entire process that writes the register to the AXI output pins. This change has no effect on the application, it still runs as the original AXI Lite IP.
I have asked countless times in the Vivado, Design Entry, Zynq forums and nobody has an idea of how to overcome this problem.
I have a very very early uZed. Is there any suggestions to overcome this issue.
Is there a test I can run to determine where the issue might be.
I have a very similar problem with an AXI Stream Master IP I am trying to build.