MicroZed Vivado Design Issue

I did another test this morning to be sure that what I was reporting here was accurate.  I built a brand new hardware project that included the following:

Zynq Processor
Processor Reset
AXI Interconnect with 1 master and one slave
AXI Lite with 6 registers.

I made no edits of any of the VHDL Exported the hardware and launched the SDK.

I created the following program in the SDK:

// Six Register attempt at 0x4300000
int main()
{
    init_platform();
    print("Hello World
r");
    int BaseAddress = 0x4300000;
    int i = 0;
    int offset = 0;
    int foo = 0;
    int regCount = 6;
    // Set each register to its index.
    for (i = 0; i < regCount; i++)
    {
    tHWTESTONE_mWriteReg(&BaseAddress, offset, i);
    toffset += 4;
    }
    offset = 0;
    // Write the value of each index
    for (i = 0; i < regCount; i++)
    {
    tfoo = HWTESTONE_mReadReg(&BaseAddress, offset);
    toffset += 4;
    tprintf("Write Register %d: %d
r", i, foo);
    }
    // Write to the register one past the number generated
    offset = regCount * 4;
    HWTESTONE_mWriteReg(&BaseAddress, offset, offset);
    // Read the register one past the number generated
    foo = HWTESTONE_mReadReg(&BaseAddress, offset);
    printf("Read Register %d: %d
r", regCount, foo);
    offset = 0;
    // Read all the registers including the one past
    for (i = 0; i < regCount +1; i++)
    {
    tfoo = HWTESTONE_mReadReg(&BaseAddress, offset);
    toffset += 4;
    tprintf("Read Register %d: %d
r", i, foo);
    }

    cleanup_platform();
    return 0;
}

The output from the program was:
Hello World
Write Register 0: 0
Write Register 1: 1
Write Register 2: 2
Write Register 3: 3
Write Register 4: 4
Write Register 5: 5
Read Register 6: 24
Read Register 0: 0
Read Register 1: 1
Read Register 2: 2
Read Register 3: 3
Read Register 4: 4
Read Register 5: 5
Read Register 6: 24

What we see here is that writing and reading past the last register works as any of the registers in the requested range.  Also, the writing of the register is not a wrap around into the original register range.  It is actually writing to where register 6 would be.  In the VHDL that was generated by the AXI Lite wizard the reading process is such that if a number past the end of the register bank  is read from the result should be zero, and it isn't.

The VHDL is

constant OPT_MEM_ADDR_BITS : integer := 2;

-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;

process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, axi_araddr, S_AXI_ARESETN, slv_reg_rden)

    --  loc_addr is a 3 bit vector [2 down to 0]
    variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
    begin
t-- Address decoding for reading registers
        -- loc_addr := axi_araddr(2 + 2 downto 2);
        -- Not sure of the specifics, assume it returns 3 bits in the address
tloc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
tcase loc_addr is
t    when b"000" =>
t        reg_data_out <= slv_reg0;
t      when b"001" =>
t        reg_data_out <= slv_reg1;
t      when b"010" =>
t        reg_data_out <= slv_reg2;
t      when b"011" =>
t        reg_data_out <= slv_reg3;
t      when b"100" =>
t        reg_data_out <= slv_reg4;
t      when b"101" =>
t        reg_data_out <= slv_reg5;

              -- for case b"110" and b"111"
t      when others =>
t        reg_data_out  <= (others => '0');
t    end case;
tend process;

Registers 6 and 7 should be in the others clause of the case statement.
The same is true for the write process.  I can only conjecture that the bitstream that is running on the MicroZed is not the same as that shown it the vhdl for the project. 

Also, I cn change the base address in the main program to
BaseAddress to 0x42000000 or to 0x60000000 I still get the same result.

I did another test this morning to be sure that what I was reporting here was accurate.  I built a brand new hardware project that included the following:

Zynq Processor
Processor Reset
AXI Interconnect with 1 master and one slave
AXI Lite with 6 registers.

I made no edits of any of the VHDL Exported the hardware and launched the SDK.

I created the following program in the SDK:

// Six Register attempt at 0x4300000
int main()
{
    init_platform();
    print("Hello World
r");
    int BaseAddress = 0x4300000;
    int i = 0;
    int offset = 0;
    int foo = 0;
    int regCount = 6;
    // Set each register to its index.
    for (i = 0; i < regCount; i++)
    {
    tHWTESTONE_mWriteReg(&BaseAddress, offset, i);
    toffset += 4;
    }
    offset = 0;
    // Write the value of each index
    for (i = 0; i < regCount; i++)
    {
    tfoo = HWTESTONE_mReadReg(&BaseAddress, offset);
    toffset += 4;
    tprintf("Write Register %d: %d
r", i, foo);
    }
    // Write to the register one past the number generated
    offset = regCount * 4;
    HWTESTONE_mWriteReg(&BaseAddress, offset, offset);
    // Read the register one past the number generated
    foo = HWTESTONE_mReadReg(&BaseAddress, offset);
    printf("Read Register %d: %d
r", regCount, foo);
    offset = 0;
    // Read all the registers including the one past
    for (i = 0; i < regCount +1; i++)
    {
    tfoo = HWTESTONE_mReadReg(&BaseAddress, offset);
    toffset += 4;
    tprintf("Read Register %d: %d
r", i, foo);
    }

    cleanup_platform();
    return 0;
}

The output from the program was:
Hello World
Write Register 0: 0
Write Register 1: 1
Write Register 2: 2
Write Register 3: 3
Write Register 4: 4
Write Register 5: 5
Read Register 6: 24
Read Register 0: 0
Read Register 1: 1
Read Register 2: 2
Read Register 3: 3
Read Register 4: 4
Read Register 5: 5
Read Register 6: 24

What we see here is that writing and reading past the last register works as any of the registers in the requested range.  Also, the writing of the register is not a wrap around into the original register range.  It is actually writing to where register 6 would be.  In the VHDL that was generated by the AXI Lite wizard the reading process is such that if a number past the end of the register bank  is read from the result should be zero, and it isn't.

The VHDL is

constant OPT_MEM_ADDR_BITS : integer := 2;

-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;

process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, axi_araddr, S_AXI_ARESETN, slv_reg_rden)

    --  loc_addr is a 3 bit vector [2 down to 0]
    variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
    begin
t-- Address decoding for reading registers
        -- loc_addr := axi_araddr(2 + 2 downto 2);
        -- Not sure of the specifics, assume it returns 3 bits in the address
tloc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
tcase loc_addr is
t    when b"000" =>
t        reg_data_out <= slv_reg0;
t      when b"001" =>
t        reg_data_out <= slv_reg1;
t      when b"010" =>
t        reg_data_out <= slv_reg2;
t      when b"011" =>
t        reg_data_out <= slv_reg3;
t      when b"100" =>
t        reg_data_out <= slv_reg4;
t      when b"101" =>
t        reg_data_out <= slv_reg5;

              -- for case b"110" and b"111"
t      when others =>
t        reg_data_out  <= (others => '0');
t    end case;
tend process;

Registers 6 and 7 should be in the others clause of the case statement.
The same is true for the write process.  I can only conjecture that the bitstream that is running on the MicroZed is not the same as that shown it the vhdl for the project. 

Also, I cn change the base address in the main program to
BaseAddress to 0x42000000 or to 0x60000000 I still get the same result.