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MicroZed Vivado Design Issue

raymadigan

I am not sure what to do at this point.  I  have tried everything I can think of except a new MicroZed board.

I have a design that uses a custom AXI Lite IP.   Basically I want to allocate N registers and have N/2 be read/write and the other N/2 be read only.  The read only registers will be written to by my application. 

I have build the design and none of my changes have any effect when I run the application on my uZed.  I have commented out the entire process that writes the register to the AXI output pins.  This change has no effect on the application, it still runs as the original AXI Lite IP.

I have asked countless times in the Vivado, Design Entry, Zynq forums and nobody has an idea of how to overcome this problem.

I have a very very early uZed.  Is there any suggestions to overcome this issue.

Is there a test I can run to determine where the issue might be.

I have a very similar problem with an AXI Stream Master IP I am trying to build.

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    I would recommend that you not let SDK automatically update the hardware. With each new hardware platform, I would export to a different , versioned directory. Once in SDK with that hardware platform, then generate the BSP, then import your previous code projects from the prior directory.

    Bryan

  • 0 in reply to bhfletcher

    I will give that a try, I really hope I can find something I am doing wrong that will let me get past this.  One thing I don't understand is that I created a fresh project with the already modified VHDL, I exported the hardware and created a brand new SDK project with the new hardware definition.  This had the same issue as all of the others did. 

    I will try some variations of this process this morning and see if the results are different.

    I do appreciate your help.

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  • 0 in reply to bhfletcher

    I will give that a try, I really hope I can find something I am doing wrong that will let me get past this.  One thing I don't understand is that I created a fresh project with the already modified VHDL, I exported the hardware and created a brand new SDK project with the new hardware definition.  This had the same issue as all of the others did. 

    I will try some variations of this process this morning and see if the results are different.

    I do appreciate your help.

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