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MicroZed Vivado Design Issue

raymadigan

I am not sure what to do at this point.  I  have tried everything I can think of except a new MicroZed board.

I have a design that uses a custom AXI Lite IP.   Basically I want to allocate N registers and have N/2 be read/write and the other N/2 be read only.  The read only registers will be written to by my application. 

I have build the design and none of my changes have any effect when I run the application on my uZed.  I have commented out the entire process that writes the register to the AXI output pins.  This change has no effect on the application, it still runs as the original AXI Lite IP.

I have asked countless times in the Vivado, Design Entry, Zynq forums and nobody has an idea of how to overcome this problem.

I have a very very early uZed.  Is there any suggestions to overcome this issue.

Is there a test I can run to determine where the issue might be.

I have a very similar problem with an AXI Stream Master IP I am trying to build.

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  • 0

    Have you looked at this in simulation?

    You might try reading/writing a dual-port blockRAM in the fabric first before getting the custom IP to work.

    Also, after you make changes in Vivado, how do you ensure the new hardware platform is being updated in SDK?

     

    BryanA

  • 0 in reply to bhfletcher

    I have run many examples with stock IP, I have an example of using DMA to write to and read from an AXI Stream FIFO.  I will do a dual port block ram to be sure I cam make that work.

    I have tried several alternatives.  When I change the VHDL in the project in vivado, I run synthesis, ..., and generate Bitstream.  I then export the Hardware and the SDK automatically recognizes the bitstream has changed rebuild the board support for the project.

    Alternatively, I have built a project with the VHDL that has the commented out process and it still acts like the Base IP. 

    The first customization I did was really simple, I forced the read of a register to output zero by replacing the write to the output signal to be (others => '0').

    I don't know how to tell what is actually written to the fabric.  Are there SDK calls to ask versioning information?

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  • 0 in reply to bhfletcher

    I have run many examples with stock IP, I have an example of using DMA to write to and read from an AXI Stream FIFO.  I will do a dual port block ram to be sure I cam make that work.

    I have tried several alternatives.  When I change the VHDL in the project in vivado, I run synthesis, ..., and generate Bitstream.  I then export the Hardware and the SDK automatically recognizes the bitstream has changed rebuild the board support for the project.

    Alternatively, I have built a project with the VHDL that has the commented out process and it still acts like the Base IP. 

    The first customization I did was really simple, I forced the read of a register to output zero by replacing the write to the output signal to be (others => '0').

    I don't know how to tell what is actually written to the fabric.  Are there SDK calls to ask versioning information?

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