Negative Timing Slack using MicroZed Board Defintion File in Vivado 2017.1

Question

When upgrading to Vivado 2017.1, using the Microzed Board definition file for 2016.4 I get an critical warning on the ddr interface.

The critical warning is:

PCW_UI_PARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.073. PS_DDR interfaces might fail when entering negative DQS skew values.

There is also a warning on DELAY_1 -0.072.

These critical warnings result in negative timing slack.

Any suggestions on what should to do about this error. I'm tempted to ignore it, but I don't want to miss any timing issues I might create in my code.

jafoste4 · Accepted Answer

Hi Matt, Here is why I believe you are having an issue. Going from Vivado 2015.2 and earlier to 2015.3 and later, the board definition format changed. I believe the project you tried to port from 2015.1 to 2017.1 had some reference to the old board definition files and couldn't properly port them over. My suggestion would be to generate the project from scratch in Vivado 2017.1 with the proper board definition files. That should solve your issue. --Josh