Negative Timing Slack using MicroZed Board Defintion File in Vivado 2017.1

You can recreate this problem by creating a new project in Vivado 2017.1. Select the Microzed 7010 board. Then create a block diagram and add a PS. Autoconnect the DDR. Then build it and these warnings will come up.

Hello Matty,

I followed the steps you outlined above and was unable to recreate your issue. Please make sure you are using the board defeniton files labeled "MicroZed Board Definition Install for Vivado 2015.3, 2015.4, 2016.1, 2016.2, 2016.3, 2016.4" located at http://zedboard.org/support/documentation/1519

Also make sure when you downloaded the file you unzipped it properly, I personally use 7-Zip to unzip my files. Do this to avoid any corruption issues.

Regards,

Josh

Hi Josh,

Thanks for looking into this. I just reran it with the right definition file and I could not recreate the issue. I will post again if i see it again and can figure out a better way to recreate it. Maybe i was still using the 2015.2 board definition files during the upgrade. There is another forum on this issue that might give some more details : https://forums.xilinx.com/t5/Design-Entry/Vivado-critical-warning-when-creating-hardware-wrapper/m-p/767113#M13539

Thanks again,

Matt

I was able to recreate the problem again.

First I created a system in Vivado 2015.2 with a PS and block automation to connect up the DDR, just like in my above comment. I built this system no problem. I used the 2015.1 Board definition file for the microzed (v1.0 vs v1.1).

Then I opened the same project in Vivado 2017.1. It asked if I wanted to automatically upgrade the project, I said yes. It then said that my IP was out of date and wanted me to update the PS to the latest version. I updated it in the IP status tab to the latest version. During the upgrade of the PS IP, I recieved the critical warnings above. I also got a message saying the board_part definition of 1.0 was not found (which I know its not there, I only have 1.1 installed for 2017.1) - Which leads me to believe the 1.1 board preset file is fine and there is something going on behind the scenes causing the error.

Hi Matt,

Here is why I believe you are having an issue. Going from Vivado 2015.2 and earlier to 2015.3 and later, the board definition format changed. I believe the project you tried to port from 2015.1 to 2017.1 had some reference to the old board definition files and couldn't properly port them over. My suggestion would be to generate the project from scratch in Vivado 2017.1 with the proper board definition files. That should solve your issue.

--Josh

Hello All,

Is there a TCL preset file available for the MicroZed board for Vivado 2016.4?

I didn't see anything for recent version of Vivado on this page:

http://zedboard.org/support/documentation/1519

-- James

Hi James,

The board definition file is located under the Board Definition FIles section labeled "MicroZed Board Definition Install for Vivado 2015.3, 2015.4, 2016.1, 2016.2, 2016.3, 2016.4". Unfortunatly we do not have a TCL script you can run to install it. You must place the unzipped file in the C:\Xilinx\Vivado\2016.4\data\boards\board_files location

--Josh

Hi Josh,

Thanks for the reply.

I did get the board definition file for the MicroZed installed correctly.

I was looking for a presets TCL file to configure things like the what is mentioned in other tutorials like with the Xilinx development boards.  However, as I now understand it, it isn't needed, and the defaults included in the board definition directory should be sufficient.

Thanks,

James

Hi Josh,

Sorry about my delayed response here. I had a couple of issues going on. Regenerating the project from scratch fixed my issues related to the new Board definition file. Thank you. I'm still getting the block diagram critical warning from Vivado that I mentioned earlier, but I was able to use the design on the microzed with no issues, so I think its just a Vivado issue that it doesn't like those negative values for whatever reason.

Thanks for all your help!

Regards,

Matt

Hi everyone,

I also use vivado version  2017.4 and when i validate my design i get the following error: PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.009 . PS DDR interfaces might fail when entering negative DQS skew values

In the previuos project at my work i usde this version of vivado, but currently i work at home with a zedboard, what would be the best solution reinstall a lower version of viavdo or any other tip ?

Thanks in advance,

Mary