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MicroZed Hardware Design Negative Timing Slack using MicroZed Board Defintion File in Vivado 2017.1
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Negative Timing Slack using MicroZed Board Defintion File in Vivado 2017.1

Former Member
Former Member over 8 years ago

When upgrading to Vivado 2017.1, using the Microzed Board definition file for 2016.4 I get an critical warning on the ddr interface.

The critical warning is:

PCW_UI_PARAM_DDR_DQS_TO_CLK_DELAY_0 has negative value -0.073. PS_DDR interfaces might fail when entering negative DQS skew values.

There is also a warning on DELAY_1 -0.072.

These critical warnings result in negative timing slack.

Any suggestions on what should to do about this error. I'm tempted to ignore it, but I don't want to miss any timing issues I might create in my code.

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  • jafoste4
    0 jafoste4 over 8 years ago

    Hi James,

    The board definition file is located under the Board Definition FIles section labeled "MicroZed Board Definition Install for Vivado 2015.3, 2015.4, 2016.1, 2016.2, 2016.3, 2016.4". Unfortunatly we do not have a TCL script you can run to install it. You must place the unzipped file in the C:\Xilinx\Vivado\2016.4\data\boards\board_files location

    --Josh

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  • james.graves
    0 james.graves over 8 years ago in reply to jafoste4

    Hi Josh,

     

    Thanks for the reply.

     

    I did get the board definition file for the MicroZed installed correctly.

     

    I was looking for a presets TCL file to configure things like the what is mentioned in other tutorials like with the Xilinx development boards.  However, as I now understand it, it isn't needed, and the defaults included in the board definition directory should be sufficient.

     

    Thanks,

     

    James

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  • james.graves
    0 james.graves over 8 years ago in reply to jafoste4

    Hi Josh,

     

    Thanks for the reply.

     

    I did get the board definition file for the MicroZed installed correctly.

     

    I was looking for a presets TCL file to configure things like the what is mentioned in other tutorials like with the Xilinx development boards.  However, as I now understand it, it isn't needed, and the defaults included in the board definition directory should be sufficient.

     

    Thanks,

     

    James

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