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PWM and Timer capture implementation on Microzed boards

pwagre

Hello,

 

We have some technically query’s with regarding to implementation of certain peripherals in ZynQ 7020 based Microzed development board.

 

We have requirement to implement 11 PWM of 16 bit resolution

And 8 Time capture of 16 bits Resolution to measure the pulse widths of signals.

 

The 8 16-bit timer Input capture  information  is used to implement 5 PID loops, the Outputs of these PID loops will define the 11 16 bit PWM

 

Is the no of F/F or cells in Zynq 7020/7010 sufficient to implement them?

 

Thanks & regards,

 

Prashant Wagre

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    When you design multiple PWM or timer capture IO systems on an FPGA you have many options which will affect the resources used.

     

    The simplest implentation for 16 bit PWM will use a 16 bit register to hold the transition count, a 16 bit counter and a 16 bit comparator.

    If you want 11 of these you could just replicate that structure 16 times. If you want to use less resource and do not need the fastest possible speed

    you could keep the transition counts in a 16 bit wide RAM block, use a single counter and comparator and an additionbal 4 bit counter to step though the

    RAM block data.

    There are endless opportunities to trade performance against resource consumption.

     

    The Xilinx FPGAs offer very efficient ways to impement some structures so it's hard to estimate how much fabric will be used - but it is easy to synthesise and fit a small block and check.

     

     

     

    MK

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  • 0

    When you design multiple PWM or timer capture IO systems on an FPGA you have many options which will affect the resources used.

     

    The simplest implentation for 16 bit PWM will use a 16 bit register to hold the transition count, a 16 bit counter and a 16 bit comparator.

    If you want 11 of these you could just replicate that structure 16 times. If you want to use less resource and do not need the fastest possible speed

    you could keep the transition counts in a 16 bit wide RAM block, use a single counter and comparator and an additionbal 4 bit counter to step though the

    RAM block data.

    There are endless opportunities to trade performance against resource consumption.

     

    The Xilinx FPGAs offer very efficient ways to impement some structures so it's hard to estimate how much fabric will be used - but it is easy to synthesise and fit a small block and check.

     

     

     

    MK

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