Hello, I am using microzed 7010. I have to set trace delay max/min in constraints input for data coming from ADC. How to calculate these parameters?
Hello, I am using microzed 7010. I have to set trace delay max/min in constraints input for data coming from ADC. How to calculate these parameters?
Xilinx has some training material on this topic:
https://xilinx.github.io/xup_fpga_vivado_flow/lab5.html
The basic idea on the input delay analysis is to give us timing budget on FPGA/board level design. Tco is related to the clock speed. Put a number there to define the clock uncertain range. trce_dly_min/max should be from the PCB layout file.
Trce_dly_min/mac can use an estimated placeholder such as +-2.5% of the clock speed, which is normally used for high speed signal board level layout design. I assumed that MicroZed board layout followed such design constraint. Here is the board layout net length data from Avnet website: www.avnet.com/.../
You might need to convert the physical trace length into trace time/latency. Rule of thrum of trace length to time: 15~17cm/ns. (https://support.xilinx.com/s/question/0D52E00006hplPcSAI/what-do-trcedlymax-and-trcedlymin-mean-when-setting-output-delay-constraints?language=ja)
FPGA timing constraints explanation can be found from this support ticket;
https://support.xilinx.com/s/article/63174?language=en_US
Which is similar way I used for this topic.
