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How to red DDR vs BRAM

quadzilla

This is another doubtlessly naive question.  I know that you can read the BRAM by using XBram_ReadReg() and a BRAM controller.  Also that XBram_ReadReg() basically amounts to using Xil_In32() to read a memory location.

Can we do something similar to read the DDR RAM, or are we always forced to use the routines in xaxidma_bdring.c?

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    Once you have the DDR connected to the CPU via AXI Interconnect, it will be memory-mapped into the CPU's address space.

    You can then use a Xil_In32() call to get the data, or you could dereference a pointer as follows:

    // Declare a pointer with memory location 0x3000_0000, and declare an u32 to hold data

    unsigned int *punData;

    unsigned int unData;

    // Get the data at the location held by the pointer

    unData = *punData;

    unData would then contain the data from address 0x30000000

    Be aware that data in the DDR is cached.  If you are accessing DDR memory that was (only) loaded by the CPU, then it will read back correctly.

    If you are accessing data that was loaded by the PL, then you probably have to invalidate the CPU's cache before reading it to ensure you get the data loaded by the CPU, and not stale data leftover in the CPU cache.

    It looks like you are using a bare metal application, so to accomplish this, take a look at the following functions:

    void Xil_DCacheInvalidate(void);
    void Xil_DCacheInvalidateRange(INTPTR adr, u32 len);
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  • 0

    Once you have the DDR connected to the CPU via AXI Interconnect, it will be memory-mapped into the CPU's address space.

    You can then use a Xil_In32() call to get the data, or you could dereference a pointer as follows:

    // Declare a pointer with memory location 0x3000_0000, and declare an u32 to hold data

    unsigned int *punData;

    unsigned int unData;

    // Get the data at the location held by the pointer

    unData = *punData;

    unData would then contain the data from address 0x30000000

    Be aware that data in the DDR is cached.  If you are accessing DDR memory that was (only) loaded by the CPU, then it will read back correctly.

    If you are accessing data that was loaded by the PL, then you probably have to invalidate the CPU's cache before reading it to ensure you get the data loaded by the CPU, and not stale data leftover in the CPU cache.

    It looks like you are using a bare metal application, so to accomplish this, take a look at the following functions:

    void Xil_DCacheInvalidate(void);
    void Xil_DCacheInvalidateRange(INTPTR adr, u32 len);
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