Hello,
I am trying to use a Microzed board to demonstrate some ideas using the latest Vivado 2024.2 and Avnet-Tria BDF files. Unfortunately, I have not been able to get the DDR3 memory to run reliably.
First, I tried to boot Petalinux but operation was erratic. In most cases the board did not send any text to the console after pressing the reset button. I suspected the DDR3 memory so I built a Vitis bare metal application but I also found it to be very unreliable running from the DDR3 which is the default. Finally, I edited the linker script to put .data, .text and .bss in the Zynq On-Chip Memory (OCM). This boots and runs reliably.
Next, I looked at the DDR3 settings in the IP Integrator block diagram of my FPGA design. At a glance I can see that the memory size is not set correctly. The settings call out 2048Mb per chip while the chips are actually 256Mx16 = 4096Mb. In my Vitis project I can see it thinks the DDR3 is only 512MB in size. I have looked a the Microzed schematics, Rev H and Rev F, and they both have 1GB DDR3.
The DDR3 settings in my FPGA project come from the Avnet BDF file for the Microblaze. I am using https://github.com/Avnet/bdf/tree/master/microzed_7020/1.4.
I think this means there are errors in the Microblaze BDF that prevent correct operation.
