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MiniZed SW Lab 05 produces no output

embeddeddesigner

Hello fellow miniZed users!

 

I use a Windows 10 workstation with Vivado 2017.4 and Xilinx SDK 2017.4 to  program my MiniZed.  After testing the Wifi as described in the "MiniZed Getting Started Guide":

 

and getting "Tutorial 02 First Application - Hello World" working, I started working my way through the SW Labs at:

 

(I downloaded the files for SDK 2017.4).

 

In SW Lab 05, experiment 1, step 7, where you re-programmed the PL.  The blue 'Done" LED started out blue and stayed blue, and I did see the message:

  11:02:44 INFO  : FPGA configured successfully with bitstream "C:/Speedway/ZynqSW/2017_4/SDK_Workspace2/hw_platform_0/System_wrapper.bit"

 

I then plunged into experiment 2, where you download and run the Hello_Zynq application. Nothing deviates from the notes until I get to then end of step 5, where nothing appears in the Tera Term window.

 

I have gotten output on the terminal emulator in prior tests but not here. I am at a loss where to start troubleshooting this problem.

 

I will paste in that part of my SDK.log file that was written today:

 

09:03:09 INFO  : Registering command handlers for SDK TCF services

09:03:09 INFO  : Launching XSCT server: xsct.bat -interactive C:\Speedway\ZynqSW\2017_4\SDK_Workspace2\temp_xsdb_launch_script.tcl

09:03:12 INFO  : XSCT server has started successfully.

09:03:12 INFO  : Successfully done setting XSCT server connection channel 

09:03:14 INFO  : Successfully done setting SDK workspace 

11:02:41 INFO  : Connected to target on host '127.0.0.1' and port '3121'.

11:02:43 INFO  : 'targets -set -filter {jtag_cable_name =~ "Avnet MiniZed V1 1234-oj1A" && level==0} -index 1' command is executed.

11:02:44 INFO  : FPGA configured successfully with bitstream "C:/Speedway/ZynqSW/2017_4/SDK_Workspace2/hw_platform_0/System_wrapper.bit"

11:08:30 INFO  : 'targets -set -filter {jtag_cable_name =~ "Avnet MiniZed V1 1234-oj1A" && level==0} -index 1' command is executed.

11:08:30 INFO  : 'fpga -state' command is executed.

11:08:30 INFO  : Connected to target on host '127.0.0.1' and port '3121'.

11:08:30 INFO  : Jtag cable 'Avnet MiniZed V1 1234-oj1A' is selected.

11:08:30 INFO  : 'jtag frequency' command is executed.

11:08:30 INFO  : Sourcing of 'C:/Speedway/ZynqSW/2017_4/SDK_Workspace2/ZynqHW/ps7_init.tcl' is done.

11:08:30 INFO  : Context for 'APU' is selected.

11:08:30 INFO  : Hardware design information is loaded from 'C:/Speedway/ZynqSW/2017_4/SDK_Workspace2/ZynqHW/system.hdf'.

11:08:30 INFO  : 'configparams force-mem-access 1' command is executed.

11:08:30 INFO  : Context for 'APU' is selected.

11:08:30 INFO  : 'stop' command is executed.

11:08:31 INFO  : 'ps7_init' command is executed.

11:08:31 INFO  : 'ps7_post_config' command is executed.

11:08:31 INFO  : Context for processor 'ps7_cortexa9_0' is selected.

11:08:31 INFO  : Processor reset is completed for 'ps7_cortexa9_0'.

11:08:31 INFO  : Context for processor 'ps7_cortexa9_0' is selected.

11:08:31 INFO  : The application 'C:/Speedway/ZynqSW/2017_4/SDK_Workspace2/Hello_Zynq_2/Debug/Hello_Zynq_2.elf' is downloaded to processor 'ps7_cortexa9_0'.

11:08:31 INFO  : 'configparams force-mem-access 0' command is executed.

11:08:31 INFO  : ----------------XSDB Script----------------

connect -url tcp:127.0.0.1:3121

source C:/Speedway/ZynqSW/2017_4/SDK_Workspace2/ZynqHW/ps7_init.tcl

targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Avnet MiniZed V1 1234-oj1A"} -index 0

loadhw -hw C:/Speedway/ZynqSW/2017_4/SDK_Workspace2/ZynqHW/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}]

configparams force-mem-access 1

targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Avnet MiniZed V1 1234-oj1A"} -index 0

stop

ps7_init

ps7_post_config

targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Avnet MiniZed V1 1234-oj1A"} -index 0

rst -processor

targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Avnet MiniZed V1 1234-oj1A"} -index 0

dow C:/Speedway/ZynqSW/2017_4/SDK_Workspace2/Hello_Zynq_2/Debug/Hello_Zynq_2.elf

configparams force-mem-access 0

----------------End of Script----------------

 

11:08:31 INFO  : Memory regions updated for context APU

11:08:31 INFO  : Context for processor 'ps7_cortexa9_0' is selected.

11:08:31 INFO  : 'con' command is executed.

11:08:31 INFO  : ----------------XSDB Script (After Launch)----------------

targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Avnet MiniZed V1 1234-oj1A"} -index 0

con

----------------End of Script----------------

 

11:08:31 INFO  : Launch script is exported to file 'C:\Speedway\ZynqSW\2017_4\SDK_Workspace2\.sdk\launch_scripts\xilinx_c-c++_application_(system_debugger)\system_debugger_using_debug_hello_zynq_2.elf_on_local.tcl'

 

Can anyone suggest what to test to narrow the field of culprits down?

Parents

  • I'm back with an update.

     

    While waiting on an answer, I leapfrogged this lab and started trying the others.  One of them mentioned that the STDIN and STDOUT ports had to be manually assigned to ps7_uart_1 in the BSP because the wizard always defaulted them to ps7_uart_0. I then recalled that I had completed other Avnet MiniZed tutorials prior to finding the Speedway labs, and that these tutorials had directed me to create BSPs without telling me to edit them.  Both tutorials named the file standalone_bsp_0.  The uart0 BSP got this name first and the one I modified became standalone_bsp_1.  I then dug around inside and found I had created app Hello_Zynq with the wrong standalone_bsp.

     

    First I tried to modify standalone_bsp_0 to talk to the right UART but although I seemingly succeeded at changing it, the terminal remained blank. So I deleted everything and re-built both application project and BSP from scratch.  This worked.

     

    Since it came at such a high price (2 days effort), I decided to contribute this intellectual morsel to the MiniZed body of knowledge. Maybe it will help somebody else.

Reply

  • I'm back with an update.

     

    While waiting on an answer, I leapfrogged this lab and started trying the others.  One of them mentioned that the STDIN and STDOUT ports had to be manually assigned to ps7_uart_1 in the BSP because the wizard always defaulted them to ps7_uart_0. I then recalled that I had completed other Avnet MiniZed tutorials prior to finding the Speedway labs, and that these tutorials had directed me to create BSPs without telling me to edit them.  Both tutorials named the file standalone_bsp_0.  The uart0 BSP got this name first and the one I modified became standalone_bsp_1.  I then dug around inside and found I had created app Hello_Zynq with the wrong standalone_bsp.

     

    First I tried to modify standalone_bsp_0 to talk to the right UART but although I seemingly succeeded at changing it, the terminal remained blank. So I deleted everything and re-built both application project and BSP from scratch.  This worked.

     

    Since it came at such a high price (2 days effort), I decided to contribute this intellectual morsel to the MiniZed body of knowledge. Maybe it will help somebody else.

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