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GTX transceivers

Former Member

Hi..

I am working with GTX transceivers on the 7030.  I am trying to configure the GTXE2_CHANNEL_X0Y1 transceiver attached to SMA on the Carrier board using Aurora 8b10b example design.
I instantiated the aurora_example design to the processing wrapper.  This only have the zynq processing with 2 pl_clocks required in Aurora.

In the file.xdc I am doing this configuration.  I donu00B4t know if it is right,
#######################################################
set_property PACKAGE_PIN U9 [get_ports GTXQ0_P]
set_false_path -through [get_pins -hier *cdc_to*]
set_property LOC GTXE2_CHANNEL_X0Y1 [get_cells aurora_module_i/aurora_8b10b_0_i/U0/gt_wrapper_i/aurora_8b10b_0_multi_gt_i/gt0_aurora_8b10b_0_i/gtxe2_i]
set_property DONT_TOUCH true [get_cells ProcessingSystem_i]
set_property DONT_TOUCH true [get_cells ProcessingSystem_i/processing_system7_0]
set_property DONT_TOUCH true [get_cells ProcessingSystem_i/processing_system7_0/inst]
set_property DONT_TOUCH true [get_cells ProcessingSystem_i/util_ds_buf_0]
set_property PACKAGE_PIN Y8 [get_ports RXN]
set_property PACKAGE_PIN W8 [get_ports RXP]
set_property PACKAGE_PIN Y4 [get_ports TXN]
set_property PACKAGE_PIN W4 [get_ports TXP]

#######################################################

I got this  error in the implementation, and I have no idea what is the reason:

[Place 30-378] Input pin of input buffer Communication_block/aurora_module_i/U0/clock_module_i/init_clk_ibufg_i has an illegal connection to a logic constant value.
[Place 30-99] Placer failed with error: 'Implementation Feasibility check failed, Please see the previously displayed individual error or warning messages for more details.'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.

Please help


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  • 0

    Hi there,

    -what is your clock source?  If you are using the PS for clocks for the Aurora design, what is driving the MGTClock pin?
    -You do not HAVE to put the constraint in there, but it is highly recommended in order to force the place and route to properly prioritize fabric resources during place and route
    -The MGT pins are hard pins, just as the MGT TX/RX pins are.  I do not think you need to define them in the XDC
    -What is the configuration you are using for the IBERT design?  Clock Input Freq., Clock input Pin (0 or 1), expected data rate?
    If errors is 0e0, then you are not getting errors.  That is a good thing.  What is more important is the BER.  WHat does that show?  I know you said you can't see BER result, but what do you mean?  The cell in the column is empty?  It is too big?  Too Small?
    -does the IBERT design say it has established link?
    -Have you connected the TX_P to RX_P and TX_N to RX_N?
    -are your cables rated for the speed that you are running?

    You can view this series of tech tips, which will help SHOW you what I mean and also help walk you through double checking all the little things.
    Go to: http://picozed.org/support/trainings-and-videos
    Search for:
    Tech Tip - Transceiver Tools 101: Intro to IBERT
    Tech Tip - Transceiver Tools 102: We have an IBERT bit stream, now what?
    Tech Tip - Transceiver Tools 103: Now that we are running, what are all these adjustments?
    Tech Tip - Transceiver Tools 104: Getting More Margin

    I think the one that is going to help you the most is 102 - which will help double check all the connections and setup.  Then you can proceed through the rest of the videos.  The last video walks you through how to get an EYE-Diagram, which will give us a good indication about what is going on.

    --Dan

Reply
  • 0

    Hi there,

    -what is your clock source?  If you are using the PS for clocks for the Aurora design, what is driving the MGTClock pin?
    -You do not HAVE to put the constraint in there, but it is highly recommended in order to force the place and route to properly prioritize fabric resources during place and route
    -The MGT pins are hard pins, just as the MGT TX/RX pins are.  I do not think you need to define them in the XDC
    -What is the configuration you are using for the IBERT design?  Clock Input Freq., Clock input Pin (0 or 1), expected data rate?
    If errors is 0e0, then you are not getting errors.  That is a good thing.  What is more important is the BER.  WHat does that show?  I know you said you can't see BER result, but what do you mean?  The cell in the column is empty?  It is too big?  Too Small?
    -does the IBERT design say it has established link?
    -Have you connected the TX_P to RX_P and TX_N to RX_N?
    -are your cables rated for the speed that you are running?

    You can view this series of tech tips, which will help SHOW you what I mean and also help walk you through double checking all the little things.
    Go to: http://picozed.org/support/trainings-and-videos
    Search for:
    Tech Tip - Transceiver Tools 101: Intro to IBERT
    Tech Tip - Transceiver Tools 102: We have an IBERT bit stream, now what?
    Tech Tip - Transceiver Tools 103: Now that we are running, what are all these adjustments?
    Tech Tip - Transceiver Tools 104: Getting More Margin

    I think the one that is going to help you the most is 102 - which will help double check all the connections and setup.  Then you can proceed through the rest of the videos.  The last video walks you through how to get an EYE-Diagram, which will give us a good indication about what is going on.

    --Dan

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