GTX transceivers

Hi there,

From the error message, it seems that you have a constant driving the clock input.
Check that you have a clock input and are NOT passing the clock through any sort of constant or buffer that might logically turn the clock into a constant.

Which Aurora example design are you using as your guide?

--Dan

Hello Dan

I am using Aurora 8b10b example_design.  I am using the PS only for getting the clocks required for Aurora:  INIT_ClK_N, INIT_CLOCK_P and DRP_CLK_IN.  For the differential init_clock I used a Utility Differential IO Buffer (OBUF_DS_P and OBUF_DS_N outputs).

Thanks for the help

Do I have to put in the <file>.xdc the constrain  for the gtx module connected for SMA port ????. In this case I am using the X0Y1

set_property LOC GTXE2_CHANNEL_X0Y1 [get_cells aurora_module_i/aurora_8b10b_0_i/U0/gt_wrapper_i/aurora_8b10b_0_multi_gt_i/gt0_aurora_8b10b_0_i/gtxe2_i]

Hi Dan

also my question is if, Do I have to use set_property XDC command to constrain the location of the GT reference clock pins ?
Thanks a lot

Please help

I am running IBERT module with ZC030, the results looks right, but I canu00B4t see BER result, it does not show any data.
, I am using the transceiver connected to SMA.. and the Errors are show as 0E0.

Thanks

Hi there,

-what is your clock source?  If you are using the PS for clocks for the Aurora design, what is driving the MGTClock pin?
-You do not HAVE to put the constraint in there, but it is highly recommended in order to force the place and route to properly prioritize fabric resources during place and route
-The MGT pins are hard pins, just as the MGT TX/RX pins are.  I do not think you need to define them in the XDC
-What is the configuration you are using for the IBERT design?  Clock Input Freq., Clock input Pin (0 or 1), expected data rate?
If errors is 0e0, then you are not getting errors.  That is a good thing.  What is more important is the BER.  WHat does that show?  I know you said you can't see BER result, but what do you mean?  The cell in the column is empty?  It is too big?  Too Small?
-does the IBERT design say it has established link?
-Have you connected the TX_P to RX_P and TX_N to RX_N?
-are your cables rated for the speed that you are running?

You can view this series of tech tips, which will help SHOW you what I mean and also help walk you through double checking all the little things.
Go to: http://picozed.org/support/trainings-and-videos
Search for:
Tech Tip - Transceiver Tools 101: Intro to IBERT
Tech Tip - Transceiver Tools 102: We have an IBERT bit stream, now what?
Tech Tip - Transceiver Tools 103: Now that we are running, what are all these adjustments?
Tech Tip - Transceiver Tools 104: Getting More Margin

I think the one that is going to help you the most is 102 - which will help double check all the connections and setup.  Then you can proceed through the rest of the videos.  The last video walks you through how to get an EYE-Diagram, which will give us a good indication about what is going on.

--Dan

Also,

IBERT will take care of all the constraints for youl

The only thing is will not account for is the SFP Laser Enable pin.  I am working on an automated design that will do this for you.  You are using a PicoZed 7030?  I just want to ensure I am pointing you to the proper source material!

--Dan

Hi Dan
Aurora
I am using PS clock for the differential clock (INIT_ClK_N, INIT_CLOCK_P) and DRP_CLK_IN both 50Mhz.  These are required for Aurora module.
For the  MGTClock  I am connecting  to MGTREFCLK0_P and MGTREFCLK0_N (U9, V9).
---------------------------------------------
IBERT
Yes, I am using PicoZed 7030, with the FMC Card.
I have followed all the steps in the videos and simulated using Vivado 2015.1 and 2014.4, but the results are the same.
- I am using 3.125 Gbps and Refclk 250MHz.. For the FMC card SW9 and SW10  in OFF OFF OFF ON ON OFF positions for setting 250 MHz.
- In Refclk Selection I put MGTREFCLK1 112 with QUAD112 1 and DIFF SSTL12 Standard.
- The link is established also it shows Locked.. When I program the board, it founds the physical SMA link connection.

-The BER column is empty.
- I did the same test for Kintex 7, and I am having the same problem  (BER column is empty), and also Errors column is 0E0 for the SMA.
- Of course I connected the cables (TXN - RXN) and (TXP - RXP)
I havenu00B4t rated my cables for this speed. Could be the reason for not getting BER result even when Errors are 0E0 ??

Thanks a lot

Unless you mistyped, I think I found your issue.
If you are using a clock on MDTREFCLK0, you need to select that clock input when walking through the configuration.  For the videos, I chose to use the onboard clock.
If your cables are not rated for this speed, you will likely see too many errors and struggle getting link.  From your description, I do not think that the speed rating of the cables is the issue.  However, I have seen similar issues when using a BAD cable.  At these rates, it does not take much to make a cable not function well.

When you tested with the Kintex 7, did you use the same cables?

What are you using for the JTAG connector?

It seems that you have the configuration setup properly for the onboard clock.
*Ensure that the Protocol Selection tab, you choose MGTREFCLK1 112 with a Custom 1 / 3.125 Gbps protocol.
*In the Clock settings tab, choose Quad112 1 from the pull down under Source.  The I/O standard should grey out.  If it does not, single click it.  This might not do anything, but that is what I typically do.

Since you are not seeing any connection errors over JTAG, there must be SOME kind of clock.  This list is more to double check your setup:
*Please check that there is NO jumper on JP6 (to the left of the SW9 and SW10), this selects the clock input source mux (see sheet 3 of the schematic)
*Since you have a 7030 based PicoZed, ensure there are NO jumpers installed on CON2.  If you select anything except 1.8V this will damage the PicoZed 7030.
*try different coax cables - it is possible that you have a bad cable (I have experienced this)
*Make sure the coax cables are SNUG, if not you could have issues from that
**having Link show only says that there are enough bits flowing, the device knows something is probably there, if you do not have grounding caps on the various connectors, the capacitive effect of the board can cause this

In video 104, I describe more of the tweaking features.  You can try clicking the inject error button for the SMA channel.  This will force errors into the stream.  If this does not work, then we need to ensure the transceivers are working.

At this point, let's enable the loopback (see video 103 around 2:25 seconds).  Try the Near End PCS and then Near End PMA.
*If you enable Near End PCS and you do not see the everything start to work, I would delete the design and start over.  Near End PCS loops back the transceiver data digitally.  If this does not work, nothing will.
*Using Near End PMA will allow you to test the Zynq transceivers up through the analog part of the chip, without leaving the chip.  This will ensure that the chip is good.

If these both check out as AOK, I would then unseat and reseat the PicoZed on your carrier card as well as change your cables (if you have not already).

Please let me know how this helps.

--Dan

Hi Dan

-Yes, I used the same cable for testing Kintex 7.
-For JTAG connector in the FMC Carrier I am using HS2 Rev. A
-I am using the configuration that you are describing.
-I donu00B4t use jumper in JP6 neither CON2.
-I tried different cables,  and the problem is the same. I made sure the coax cable were snug. 
- When I inject error using the button, I can see error count increased in the Error Column.
-Near End PCS and then Near End PMA works, using all 4 transceivers.
-Also I build a new project in Vivado 2014.4 with Ubuntu, and the result is the same.
However I found out that in the RX Properties Window, RX_BER had values and are changed. but BER, TXUSERCLK, TXUSERCLK2, RXUSERCLK, TXUSERCLK2 columns are always empty.
These are the data display it:
NametValue
CLASSthw_sio_rx
DISPLAY_NAMEtMGT_X0Y1/RX
DRP.ES_CONTROLt00
DRP.ES_CONTROL_STATUSt1
DRP.ES_ERRDET_ENt0
DRP.ES_ERROR_COUNTt0000
DRP.ES_EYE_SCAN_ENt1
DRP.ES_HORZ_OFFSETt000
DRP.ES_PMA_CFGt000
DRP.ES_PRESCALEt00
DRP.ES_QUALIFIERt00000000000000000000
DRP.ES_QUAL_MASKt00000000000000000000
DRP.ES_RDATAt00000000000000000000
DRP.ES_SAMPLE_COUNTt0000
DRP.ES_SDATAt00000000000000000000
DRP.ES_SDATA_MASKt00000000000000000000
DRP.ES_UT_SIGNt0
DRP.ES_VERT_OFFSETt000
DRP.FTS_DESKEW_SEQ_ENABLEtF
DRP.FTS_LANE_DESKEW_CFGtF
DRP.FTS_LANE_DESKEW_ENt0
DRP.RXBUFRESET_TIMEt01
DRP.RXBUF_ADDR_MODEt1
DRP.RXBUF_EIDLE_HI_CNTt8
DRP.RXBUF_EIDLE_LO_CNTt0
DRP.RXBUF_ENt1
DRP.RXBUF_RESET_ON_CB_CHANGEt1
DRP.RXBUF_RESET_ON_COMMAALIGNt0
DRP.RXBUF_RESET_ON_EIDLEt0
DRP.RXBUF_RESET_ON_RATE_CHANGEt1
DRP.RXBUF_THRESH_OVFLWt3D
DRP.RXBUF_THRESH_OVRDt0
DRP.RXBUF_THRESH_UNDFLWt04
DRP.RXCDRFREQRESET_TIMEt01
DRP.RXCDRPHRESET_TIMEt01
DRP.RXCDR_CFGt03800023FF40200020
DRP.RXCDR_FR_RESET_ON_EIDLEt0
DRP.RXCDR_HOLD_DURING_EIDLEt0
DRP.RXCDR_LOCK_CFGt15
DRP.RXCDR_PH_RESET_ON_EIDLEt0
DRP.RXDFELPMRESET_TIMEt0F
DRP.RXDLY_CFGt001F
DRP.RXDLY_LCFGt030
DRP.RXDLY_TAP_CFGt0000
DRP.RXGEARBOX_ENt0
DRP.RXISCANRESET_TIMEt01
DRP.RXLPM_HF_CFGt00F0
DRP.RXLPM_LF_CFGt00F0
DRP.RXOOB_CFGt06
DRP.RXOUT_DIVt1
DRP.RXPCSRESET_TIMEt01
DRP.RXPHDLY_CFGt084020
DRP.RXPH_CFGt000000
DRP.RXPH_MONITOR_SELt00
DRP.RXPMARESET_TIMEt03
DRP.RXPRBS_ERR_LOOPBACKt0
DRP.RXSLIDE_AUTO_WAITt7
DRP.RXSLIDE_MODEt0
DRP.RX_BIAS_CFGt004
DRP.RX_BUFFER_CFGt00
DRP.RX_CLK25_DIVt09
DRP.RX_CLKMUX_PDt1
DRP.RX_CM_SELt3
DRP.RX_CM_TRIMt4
DRP.RX_DATA_WIDTHt4
DRP.RX_DDI_SELt00
DRP.RX_DEBUG_CFGt000
DRP.RX_DEFER_RESET_BUF_ENt1
DRP.RX_DFE_CTLE_STAGE1t8
DRP.RX_DFE_CTLE_STAGE2t3
DRP.RX_DFE_CTLE_STAGE3t0
DRP.RX_DFE_GAIN_CFGt020FEA
DRP.RX_DFE_H2_CFGt000
DRP.RX_DFE_H3_CFGt040
DRP.RX_DFE_H4_CFGt0F0
DRP.RX_DFE_H5_CFGt0E0
DRP.RX_DFE_KL_CFG2t3010D90C
DRP.RX_DFE_KL_CFGt00FE
DRP.RX_DFE_LPM_CFGt0954
DRP.RX_DFE_LPM_HOLD_DURING_EIDLEt0
DRP.RX_DFE_UT_CFGt11E00
DRP.RX_DFE_VP_CFGt03F03
DRP.RX_DFE_XYD_CFGt0000
DRP.RX_DISPERR_SEQ_MATCHt1
DRP.RX_INT_DATAWIDTHt1
DRP.RX_OS_CFGt0080
DRP.RX_SIG_VALID_DLYt09
DRP.RX_XCLK_SELt0
DRP.TXBUF_RESET_ON_RATE_CHANGEt0
DRP.TXPCSRESET_TIMEt01
DRP.TXPMARESET_TIMEt01
DRP.TX_LOOPBACK_DRIVE_HIZt0
DRP.TX_RXDETECT_CFGt1832
DRP.TX_RXDETECT_REFt4
ES_HORZ_MIN_MAXt64
LINE_RATEt3.125
LOGIC.ERRBIT_COUNTt000000000000
LOGIC.GT_SOURCES_SYSCLKt0
LOGIC.LINKt1
LOGIC.MGT_ERRCNT_RESET_CTRLt0
LOGIC.MGT_ERRCNT_RESET_STATt0
LOGIC.MGT_RESET_CTRLt0
LOGIC.MGT_RESET_STATt0
LOGIC.RXPAT_IDt1
LOGIC.RXRECCLK_FREQ_CNTt0F9F
LOGIC.RXRECCLK_FREQ_TUNEt4000
LOGIC.RXUSRCLK2_FREQ_CNTt0FA0
LOGIC.RXUSRCLK2_FREQ_TUNEt4000
LOGIC.RXUSRCLK_FREQ_CNTt0FA0
LOGIC.RXUSRCLK_FREQ_TUNEt4000
LOGIC.RXWORD_COUNTt000844861ACB
LOGIC.RX_DCM_LOCKt1
LOGIC.RX_DCM_RESET_CTRLt0
LOGIC.RX_DCM_RESET_STATt0
LOGIC.RX_FRAMEDt0
LOGIC.TX_DCM_RESET_CTRLt0
LOGIC.TX_DCM_RESET_STATt1
LOOPBACKtNone
NAMEtlocalhost/xilinx_tcf/Digilent/210249982432/1_1/IBERT/Quad_112/MGT_X0Y1/RX
PARENTtlocalhost/xilinx_tcf/Digilent/210249982432/1_1/IBERT/Quad_112/MGT_X0Y1
PORT.CFGRESETt0
PORT.CPLLRESETt0
PORT.EYESCANDATAERRORt0
PORT.EYESCANMODEt0
PORT.EYESCANRESETt0
PORT.EYESCANTRIGGERt0
PORT.GTRESETSELt0
PORT.GTRXRESETt0
PORT.GTTXRESETt0
PORT.LOOPBACKt0
PORT.RESETOVRDt0
PORT.RX8B10BENt0
PORT.RXBUFRESETt0
PORT.RXBUFSTATUSt0
PORT.RXBYTEISALIGNEDt0
PORT.RXBYTEREALIGNt0
PORT.RXCDRFREQRESETt0
PORT.RXCDRHOLDt0
PORT.RXCDRLOCKt1
PORT.RXCDROVRDENt0
PORT.RXCDRRESETt0
PORT.RXCDRRESETRSVt0
PORT.RXCHANBONDSEQt0
PORT.RXCHANISALIGNEDt1
PORT.RXCHANREALIGNt0
PORT.RXCHARISCOMMAt00
PORT.RXCHARISKt00
PORT.RXCHBONDENt0
PORT.RXCHBONDIt10
PORT.RXCHBONDLEVELt0
PORT.RXCHBONDMASTERt0
PORT.RXCHBONDOt00
PORT.RXCHBONDSLAVEt0
PORT.RXCLKCORCNTt0
PORT.RXCOMINITDETt0
PORT.RXCOMMADETt0
PORT.RXCOMMADETENt0
PORT.RXCOMSASDETt0
PORT.RXCOMWAKEDETt0
PORT.RXDATAVALIDt1
PORT.RXDDIENt0
PORT.RXDFEAGCHOLDt0
PORT.RXDFEAGCOVRDENt0
PORT.RXDFECM1ENt0
PORT.RXDFELFHOLDt0
PORT.RXDFELFOVRDENt0
PORT.RXDFELPMRESETt0
PORT.RXDFETAP2HOLDt0
PORT.RXDFETAP2OVRDENt0
PORT.RXDFETAP3HOLDt0
PORT.RXDFETAP3OVRDENt0
PORT.RXDFETAP4HOLDt0
PORT.RXDFETAP4OVRDENt0
PORT.RXDFETAP5HOLDt0
PORT.RXDFETAP5OVRDENt0
PORT.RXDFEUTHOLDt0
PORT.RXDFEUTOVRDENt0
PORT.RXDFEVPHOLDt0
PORT.RXDFEVPOVRDENt0
PORT.RXDFEVSENt0
PORT.RXDFEXYDENt0
PORT.RXDFEXYDHOLDt0
PORT.RXDFEXYDOVRDENt0
PORT.RXDISPERRt00
PORT.RXDLYBYPASSt1
PORT.RXDLYENt0
PORT.RXDLYOVRDENt0
PORT.RXDLYSRESETt0
PORT.RXDLYSRESETDONEt0
PORT.RXELECIDLEt1
PORT.RXELECIDLEMODEt0
PORT.RXGEARBOXSLIPt0
PORT.RXHEADERt0
PORT.RXHEADERVALIDt0
PORT.RXLPMENt0
PORT.RXLPMHFHOLDt0
PORT.RXLPMHFOVRDENt0
PORT.RXLPMLFHOLDt0
PORT.RXLPMLFKLOVRDENt0
PORT.RXMCOMMAALIGNENt0
PORT.RXMONITOROUTt7F
PORT.RXMONITORSELt0
PORT.RXNOTINTABLEtFF
PORT.RXOOBRESETt0
PORT.RXOSHOLDt0
PORT.RXOSOVRDENt0
PORT.RXOUTCLKFABRICt1
PORT.RXOUTCLKPCSt0
PORT.RXOUTCLKSELt1
PORT.RXPCOMMAALIGNENt0
PORT.RXPCSRESETt0
PORT.RXPDt0
PORT.RXPHALIGNt0
PORT.RXPHALIGNDONEt0
PORT.RXPHALIGNENt0
PORT.RXPHDLYPDt0
PORT.RXPHDLYRESETt0
PORT.RXPHMONITORt00
PORT.RXPHOVRDENt0
PORT.RXPHSLIPMONITORt09
PORT.RXPMARESETt0
PORT.RXPOLARITYt0
PORT.RXPRBSCNTRESETt0
PORT.RXPRBSERRt0
PORT.RXPRBSSELt0
PORT.RXQPIENt0
PORT.RXQPISENNt0
PORT.RXQPISENPt0
PORT.RXRATEt0
PORT.RXRATEDONEt0
PORT.RXRESETDONEt1
PORT.RXSLIDEt0
PORT.RXSTARTOFSEQt0
PORT.RXSTATUSt4
PORT.RXSYSCLKSELt3
PORT.RXUSERRDYt1
PORT.RXVALIDt0
PORT.TXDETECTRXt0
PORT.TXDLYSRESETt0
PORT.TXDLYSRESETDONEt0
PORT.TXPCSRESETt0
PORT.TXPHDLYRESETt0
PORT.TXPMARESETt0
PORT.TXRESETDONEt1
RXDFEENABLEDt1
RXOUTCLKSELtRXOUTCLKPCS
RXOUT_DIVt2
RXPLLtQPLL
RXRATEtUse RX_OUT_DIV
RXTERMt900 mV
RXTERMMODEtProgrammable
RXUSRCLK2_FREQt97,680664
RXUSRCLK_FREQt97,680664
RX_BERt8,8004921487762598e-13
RX_DATA_WIDTHt32
RX_DFE_CTLEt
RX_INTERNAL_DATAPATHt4-byte
RX_PATTERNtPRBS 7-bit
RX_PLLtlocalhost/xilinx_tcf/Digilent/210249982432/1_1/IBERT/Quad_112/COMMON_X0Y0/QPLL_0
RX_RECEIVED_BIT_COUNTt1136300087648
STATUSt3.125 Gbps

When I tried Create Scan, also doesnu00B4t wok.
At this point, no idea what else I could do ...

Do you have another suggestion please?. I appreciate a lot your kindly help.