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GTX transceivers

Former Member

Hi..

I am working with GTX transceivers on the 7030.  I am trying to configure the GTXE2_CHANNEL_X0Y1 transceiver attached to SMA on the Carrier board using Aurora 8b10b example design.
I instantiated the aurora_example design to the processing wrapper.  This only have the zynq processing with 2 pl_clocks required in Aurora.

In the file.xdc I am doing this configuration.  I donu00B4t know if it is right,
#######################################################
set_property PACKAGE_PIN U9 [get_ports GTXQ0_P]
set_false_path -through [get_pins -hier *cdc_to*]
set_property LOC GTXE2_CHANNEL_X0Y1 [get_cells aurora_module_i/aurora_8b10b_0_i/U0/gt_wrapper_i/aurora_8b10b_0_multi_gt_i/gt0_aurora_8b10b_0_i/gtxe2_i]
set_property DONT_TOUCH true [get_cells ProcessingSystem_i]
set_property DONT_TOUCH true [get_cells ProcessingSystem_i/processing_system7_0]
set_property DONT_TOUCH true [get_cells ProcessingSystem_i/processing_system7_0/inst]
set_property DONT_TOUCH true [get_cells ProcessingSystem_i/util_ds_buf_0]
set_property PACKAGE_PIN Y8 [get_ports RXN]
set_property PACKAGE_PIN W8 [get_ports RXP]
set_property PACKAGE_PIN Y4 [get_ports TXN]
set_property PACKAGE_PIN W4 [get_ports TXP]

#######################################################

I got this  error in the implementation, and I have no idea what is the reason:

[Place 30-378] Input pin of input buffer Communication_block/aurora_module_i/U0/clock_module_i/init_clk_ibufg_i has an illegal connection to a logic constant value.
[Place 30-99] Placer failed with error: 'Implementation Feasibility check failed, Please see the previously displayed individual error or warning messages for more details.'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.

Please help


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  • 0

    I received a response from one of our specialists.  He mentioned that my thinking the RXUSRCLK needing to be higher was incorrect.  Here is an excerpt from his e-mail:

    "In fact 97MHz is exactly the right frequency for those clocks. The RXUSRCLK is determined by the (serial line rate) / (Internal data width). Its mentioned on the thread that they are operating at a line rate of 3.125Gbps, and most likely they have the data width set to 32 (IBERT default setting.)

    So given all this I would expect the RXUSRCLK = 3.125G / 32 = 97.656250 MHz

    If RXUSRCLK2 is also equal to 32 then RXUSRCLK2 = RXUSRCLK.

    All of this is explained in detail in the GTX user guide.

    "

    So, I think that now that you have your regional settings changed, also armed with the above knowledge,  I think you are all set!

    Please let me know if you agree!

    --Dan

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  • 0

    I received a response from one of our specialists.  He mentioned that my thinking the RXUSRCLK needing to be higher was incorrect.  Here is an excerpt from his e-mail:

    "In fact 97MHz is exactly the right frequency for those clocks. The RXUSRCLK is determined by the (serial line rate) / (Internal data width). Its mentioned on the thread that they are operating at a line rate of 3.125Gbps, and most likely they have the data width set to 32 (IBERT default setting.)

    So given all this I would expect the RXUSRCLK = 3.125G / 32 = 97.656250 MHz

    If RXUSRCLK2 is also equal to 32 then RXUSRCLK2 = RXUSRCLK.

    All of this is explained in detail in the GTX user guide.

    "

    So, I think that now that you have your regional settings changed, also armed with the above knowledge,  I think you are all set!

    Please let me know if you agree!

    --Dan

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