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PicoZed Hardware Design 1.2V common mode LVDS
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1.2V common mode LVDS

Former Member
Former Member over 9 years ago

I am evaluating the PicoZed to interface to a sensor with a 1.2V common mode LVDS SPI bus interface (so 8 pins) and then a handful of CMOS 3.3V IO pins for control.

Assuming that a 1.8V rail voltage will work for the LVDS, I am asking if I can do this without the carrier board and using the 7010 PicoZed with PS-based IO.

Bank 500 has 8 PS IO lines on JX2 at 3.3V. This looks good for the few CMOS lines.
Bank 501 has 12 PS IO lines on JX3 at 1.8V. But can I implement differential signaling easily on the PS side, or do I need to do this with one of the PL banks?

Any thoughts?

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  • bhfletcher
    0 bhfletcher over 9 years ago

    The MIOs are not differential capable. You will need to use the PL. You could still use a SPI controller from the PS, interfaced through EMIO into the PL, with a shim to go from single-ended to differential on the PL IOs.

    Bryan

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  • drozwood90
    0 drozwood90 over 9 years ago

    To further this - relating to you questions about the bank voltages, see this Answer record from Xilinx, which indicates the bank voltages that you need to use.  Remember, if you are using HP banks (available on the 7030 part) you must only use 1.2 or 1.8V.

    http://www.xilinx.com/support/answers/43989.html

    --Dan

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