I believe there are some errors in the Design Guide (Rev 1.5). In table 5 on page 9, the 7030 FPGA pins are not mapped correctly to the JX3 pins according to the schematics (Rev B). Table 17 on page 26 seems to have it correct.
For instance, PS_MIO40_501 is connected to FPGA pin E9 and to JX3-43 according to the schematics and to Table 17. Table 5 shows it connected to JX3-39.
