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Zynq 7030

zrmireya

Hi...

I am trying to implement Aurora protocol using the GTX transeiver and I need to constrains a differential clock input for the logical part.
But, I only found 33.33Mhz PS_ckl net, and I need a 50MHz differential clk for the logical part.

I donu00B4t know what to do.. pls help

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    Hi there!
    I can try to help, but can you please answer a few questions first?
    If you are using the GTX, are you trying to source the MGT clock from the PS?  If so, this is not advisable.  There is much too much jitter with this path.
    If you need a 50MHz clock for your logic, and you are starting with the 33.333MHz PS clock, you will need to use a PLL or MCMM in order to get 50MHz.
    Am I understanding your use case?

    --Dan

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  • 0

    Hi there!
    I can try to help, but can you please answer a few questions first?
    If you are using the GTX, are you trying to source the MGT clock from the PS?  If so, this is not advisable.  There is much too much jitter with this path.
    If you need a 50MHz clock for your logic, and you are starting with the 33.333MHz PS clock, you will need to use a PLL or MCMM in order to get 50MHz.
    Am I understanding your use case?

    --Dan

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