Zynq 7030

Hi...

I am trying to implement Aurora protocol using the GTX transeiver and I need to constrains a differential clock input for the logical part.
But, I only found 33.33Mhz PS_ckl net, and I need a 50MHz differential clk for the logical part.

I donu00B4t know what to do.. pls help

0 drozwood90 over 8 years ago

Hi there!
I can try to help, but can you please answer a few questions first?
If you are using the GTX, are you trying to source the MGT clock from the PS? If so, this is not advisable. There is much too much jitter with this path.
If you need a 50MHz clock for your logic, and you are starting with the 33.333MHz PS clock, you will need to use a PLL or MCMM in order to get 50MHz.
Am I understanding your use case?

--Dan
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0 zrmireya over 8 years ago in reply to drozwood90

Hi Dan

Thanks for your help. I am using the clock for the logic part. My doubt is, if can I generate a differential clock using the PLL using the 33.333MHz PS clock, because it is what I need as entry for Aurora logic part.
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0 drozwood90 over 8 years ago

Hi there,

Are you referring to the Aurora link protocol?
http://www.xilinx.com/products/design_resources/conn_central/grouping/aurora.htm
If so, why do you need a differential clock? If you are using some other part, can you please explain? I do not see why you cannot us the PS clock to drive logic. You can just pipe that into a PLL of MCMM in the logic to derive what you need (50Mhz?).

If you need a differential clock, you can use two outputs from the PLL, or you can invert the signal in logic. I'd prefer you invert using the PLL instead (shift the output 180deg from the "p" clock).

--Dan
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