Zynq 7030

Hi...

I am trying to implement Aurora protocol using the GTX transeiver and I need to constrains a differential clock input for the logical part.
But, I only found 33.33Mhz PS_ckl net, and I need a 50MHz differential clk for the logical part.

I donu00B4t know what to do.. pls help

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0 drozwood90 over 10 years ago

Hi there,

Are you referring to the Aurora link protocol?
http://www.xilinx.com/products/design_resources/conn_central/grouping/aurora.htm
If so, why do you need a differential clock? If you are using some other part, can you please explain? I do not see why you cannot us the PS clock to drive logic. You can just pipe that into a PLL of MCMM in the logic to derive what you need (50Mhz?).

If you need a differential clock, you can use two outputs from the PLL, or you can invert the signal in logic. I'd prefer you invert using the PLL instead (shift the output 180deg from the "p" clock).

--Dan
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0 drozwood90 over 10 years ago

Hi there,

Are you referring to the Aurora link protocol?
http://www.xilinx.com/products/design_resources/conn_central/grouping/aurora.htm
If so, why do you need a differential clock? If you are using some other part, can you please explain? I do not see why you cannot us the PS clock to drive logic. You can just pipe that into a PLL of MCMM in the logic to derive what you need (50Mhz?).

If you need a differential clock, you can use two outputs from the PLL, or you can invert the signal in logic. I'd prefer you invert using the PLL instead (shift the output 180deg from the "p" clock).

--Dan
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