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PicoZed 7020 Package flight times

Former Member

Hello all,

 

Is it possible to get a copy of the picozed 7020 package flight times - specifically for the DDR3 interface nets?

Thanks!

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    Xilinx makes it possible for you to generate these for yourself. See UG899:

     

    Package Trace Length
    Instead of giving trace length data, Vivado Design Suite provides trace delay data, which is
    the most accurate way to estimate package delay.
    1. Open a design in Vivado, either RTL, netlist or implemented.
    2. Select Export > I/O Ports > CSV to see the min and max package delays for each pin.
    The min/max trace delays are also displayed in the Package Pins window for every
    package pin within two separate columns.
    Alternatively, you can select File > Export I/O ports for a CSV type spreadsheet that
    includes delays.
    3. The following TCL commands can be used is there is no project:
    link_design -part <part_number>
    write_csv <file_name>
    For Example:
    link_design -part xc7k410tffg900-2
    write_csv flight_time
     
    I have also created a TCL script that will do this as well.
     
      set part_name "xc7z020-clg400"
       
      create_project ExportPKG -part $part_name
      create_bd_design "design_1"
      generate_target all [get_files  ./ExportPKG.srcs/sources_1/bd/design_1/design_1.bd]
      make_wrapper -files [get_files ./ExportPKG.srcs/sources_1/bd/design_1/design_1.bd] -top
      add_files -norecurse ./ExportPKG.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v
      update_compile_order -fileset sources_1
      update_compile_order -fileset sim_1
      launch_runs synth_1
      wait_on_run synth_1
      open_run synth_1 -name netlist_1
      write_csv ./${part_name}.csv
     
    I am not able to attach a file here, but if you still need it, reply and I will post online somewhere.
     
    Bryan
Reply
  • 0

    Xilinx makes it possible for you to generate these for yourself. See UG899:

     

    Package Trace Length
    Instead of giving trace length data, Vivado Design Suite provides trace delay data, which is
    the most accurate way to estimate package delay.
    1. Open a design in Vivado, either RTL, netlist or implemented.
    2. Select Export > I/O Ports > CSV to see the min and max package delays for each pin.
    The min/max trace delays are also displayed in the Package Pins window for every
    package pin within two separate columns.
    Alternatively, you can select File > Export I/O ports for a CSV type spreadsheet that
    includes delays.
    3. The following TCL commands can be used is there is no project:
    link_design -part <part_number>
    write_csv <file_name>
    For Example:
    link_design -part xc7k410tffg900-2
    write_csv flight_time
     
    I have also created a TCL script that will do this as well.
     
      set part_name "xc7z020-clg400"
       
      create_project ExportPKG -part $part_name
      create_bd_design "design_1"
      generate_target all [get_files  ./ExportPKG.srcs/sources_1/bd/design_1/design_1.bd]
      make_wrapper -files [get_files ./ExportPKG.srcs/sources_1/bd/design_1/design_1.bd] -top
      add_files -norecurse ./ExportPKG.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v
      update_compile_order -fileset sources_1
      update_compile_order -fileset sim_1
      launch_runs synth_1
      wait_on_run synth_1
      open_run synth_1 -name netlist_1
      write_csv ./${part_name}.csv
     
    I am not able to attach a file here, but if you still need it, reply and I will post online somewhere.
     
    Bryan
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