I works on Picozed 7020 Carrier Card V1
my VHDL code:
You can source clock from the PS to the PL in the Zynq Processor. Please refer to this post http://zedboard.org/content/ps-clock-pl
i already used the FCLK_CLK0. I putted this CLK on input but when program my FPGA, no result.
I just want to see the FCLK_CLK0 on a output. Do you have a solution for that ?
Please take a look at these posts :