Hi,
I works on Picozed 7020 Carrier Card V1
my VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
entity led is
Port (
clk : in std_logic;
switch : in std_logic;
led : out std_logic
);
end led;
architecture behav of led is
begin
led <= clk;
end behav;
CONTRAINTS:
#OUTPUTS
set_property PACKAGE_PIN Y9 [get_ports {led}]
set_property PACKAGE_PIN V5 [get_ports {switch}]
set_property IOSTANDARD LVCMOS33 [get_ports {led}]
set_property IOSTANDARD LVCMOS33 [get_ports {switch}]
I want to see my clock on my output, but i don't know the access of PL clock. Could you give a solution pls ?
Thank u
Dass
