Hi..
I am working with GTX transceivers on the Picozed 7030 using 10GBASE-R example design for 4-lane with VIVADO 2015.1. It refers the Kintex-7 FPGA Transceiver Wizard Example Design.
In the file.xdc I am doing this configuration. I don't know if it is right,
####################################################################
create_clock -period 6.400 [get_ports Q0_CLK1_GTREFCLK_PAD_P_IN]
create_clock -period 16.667 -name drpclk_in_i [get_ports DRP_CLK_IN_P]
# User Clock Constraints
set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_txfsmresetdone_r*/CLR}]
set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_txfsmresetdone_r*/D}]
set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_rxresetdone_vio_r*/CLR}]
set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_rxresetdone_vio_r*/D}]
set_property PACKAGE_PIN U5 [get_ports Q0_CLK1_GTREFCLK_PAD_P_IN]
set_property PACKAGE_PIN V5 [get_ports Q0_CLK1_GTREFCLK_PAD_N_IN]
set_property LOC GTXE2_CHANNEL_X0Y0 [get_cells gtwizard_0_support_i/gtwizard_0_init_i/inst/gtwizard_0_i/gt0_gtwizard_0_i/gtxe2_i]
set_property LOC GTXE2_CHANNEL_X0Y1 [get_cells gtwizard_0_support_i/gtwizard_0_init_i/inst/gtwizard_0_i/gt1_gtwizard_0_i/gtxe2_i]
set_property LOC GTXE2_CHANNEL_X0Y2 [get_cells gtwizard_0_support_i/gtwizard_0_init_i/inst/gtwizard_0_i/gt2_gtwizard_0_i/gtxe2_i]
set_property LOC GTXE2_CHANNEL_X0Y3 [get_cells gtwizard_0_support_i/gtwizard_0_init_i/inst/gtwizard_0_i/gt3_gtwizard_0_i/gtxe2_i]
##---------- Set ASYNC_REG for flop which have async input ----------
##set_property ASYNC_REG TRUE [get_cells -hier -filter {name=~*gt0_frame_gen*system_reset_r_reg}]
##set_property ASYNC_REG TRUE [get_cells -hier -filter {name=~*gt0_frame_check*system_reset_r_reg}]
##set_property ASYNC_REG TRUE [get_cells -hier -filter {name=~*gt1_frame_gen*system_reset_r_reg}]
##set_property ASYNC_REG TRUE [get_cells -hier -filter {name=~*gt1_frame_check*system_reset_r_reg}]
##set_property ASYNC_REG TRUE [get_cells -hier -filter {name=~*gt2_frame_gen*system_reset_r_reg}]
##set_property ASYNC_REG TRUE [get_cells -hier -filter {name=~*gt2_frame_check*system_reset_r_reg}]
##set_property ASYNC_REG TRUE [get_cells -hier -filter {name=~*gt3_frame_gen*system_reset_r_reg}]
##set_property ASYNC_REG TRUE [get_cells -hier -filter {name=~*gt3_frame_check*system_reset_r_reg}]
##---------- Set False Path from one clock to other ----------
set_property IOSTANDARD LVDS [get_ports DRP_CLK_IN_P]
set_property IOSTANDARD LVCMOS18 [get_ports TRACK_DATA_OUT]
set_property PACKAGE_PIN U2 [get_ports DRP_CLK_IN_P]
set_property PACKAGE_PIN R8 [get_ports TRACK_DATA_OUT]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets DRPCLK_IN]
#######################################################################
I got this error in the implementation, and I have no idea what is the reason:
ERROR: [Labtools 27-1395] Unable to arm ILA 'hw_ila_5'. The core clock is slow or no core clock connected for this ILA or the ILA core may not meet timing.
ERROR: [Xicom 50-38] xicom: Core access failed. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-initialize the hardware target. Use open_hw_target to re-register the hardware device.
Please help.
--Huey
