Picozed GTX example design

Hi..

I am working with GTX transceivers on the Picozed 7030 using 10GBASE-R example design for 4-lane with VIVADO 2015.1. It refers the Kintex-7 FPGA Transceiver Wizard Example Design.

In the file.xdc I am doing this configuration. I don't know if it is right,
####################################################################
create_clock -period 6.400 [get_ports Q0_CLK1_GTREFCLK_PAD_P_IN]

create_clock -period 16.667 -name drpclk_in_i [get_ports DRP_CLK_IN_P]

# User Clock Constraints

set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_txfsmresetdone_r*/CLR}]
set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_txfsmresetdone_r*/D}]
set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_rxresetdone_vio_r*/CLR}]
set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_rxresetdone_vio_r*/D}]

set_property PACKAGE_PIN U5 [get_ports Q0_CLK1_GTREFCLK_PAD_P_IN]
set_property PACKAGE_PIN V5 [get_ports Q0_CLK1_GTREFCLK_PAD_N_IN]

set_property LOC GTXE2_CHANNEL_X0Y0 [get_cells gtwizard_0_support_i/gtwizard_0_init_i/inst/gtwizard_0_i/gt0_gtwizard_0_i/gtxe2_i]

set_property LOC GTXE2_CHANNEL_X0Y1 [get_cells gtwizard_0_support_i/gtwizard_0_init_i/inst/gtwizard_0_i/gt1_gtwizard_0_i/gtxe2_i]

set_property LOC GTXE2_CHANNEL_X0Y2 [get_cells gtwizard_0_support_i/gtwizard_0_init_i/inst/gtwizard_0_i/gt2_gtwizard_0_i/gtxe2_i]

set_property LOC GTXE2_CHANNEL_X0Y3 [get_cells gtwizard_0_support_i/gtwizard_0_init_i/inst/gtwizard_0_i/gt3_gtwizard_0_i/gtxe2_i]

##---------- Set ASYNC_REG for flop which have async input ----------
##set_property ASYNC_REG TRUE [get_cells -hier -filter {name=~*gt0_frame_gen*system_reset_r_reg}]
##set_property ASYNC_REG TRUE [get_cells -hier -filter {name=~*gt0_frame_check*system_reset_r_reg}]
##set_property ASYNC_REG TRUE [get_cells -hier -filter {name=~*gt1_frame_gen*system_reset_r_reg}]
##set_property ASYNC_REG TRUE [get_cells -hier -filter {name=~*gt1_frame_check*system_reset_r_reg}]
##set_property ASYNC_REG TRUE [get_cells -hier -filter {name=~*gt2_frame_gen*system_reset_r_reg}]
##set_property ASYNC_REG TRUE [get_cells -hier -filter {name=~*gt2_frame_check*system_reset_r_reg}]
##set_property ASYNC_REG TRUE [get_cells -hier -filter {name=~*gt3_frame_gen*system_reset_r_reg}]
##set_property ASYNC_REG TRUE [get_cells -hier -filter {name=~*gt3_frame_check*system_reset_r_reg}]

##---------- Set False Path from one clock to other ----------

set_property IOSTANDARD LVDS [get_ports DRP_CLK_IN_P]
set_property IOSTANDARD LVCMOS18 [get_ports TRACK_DATA_OUT]

set_property PACKAGE_PIN U2 [get_ports DRP_CLK_IN_P]
set_property PACKAGE_PIN R8 [get_ports TRACK_DATA_OUT]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets DRPCLK_IN]

#######################################################################
I got this error in the implementation, and I have no idea what is the reason:
ERROR: [Labtools 27-1395] Unable to arm ILA 'hw_ila_5'. The core clock is slow or no core clock connected for this ILA or the ILA core may not meet timing.
ERROR: [Xicom 50-38] xicom: Core access failed. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-initialize the hardware target. Use open_hw_target to re-register the hardware device.

Please help.

--Huey

0 Former Member over 9 years ago

the other errors:

ERROR: [Xicom 50-38] xicom: Core access failed. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-initialize the hardware target. Use open_hw_target to re-register the hardware device.
ERROR: [Xicom 50-38] xicom: Core access failed. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-initialize the hardware target. Use open_hw_target to re-register the hardware device.
ERROR: [Xicom 50-38] xicom: Core access failed. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-initialize the hardware target. Use open_hw_target to re-register the hardware device.
ERROR: [Xicom 50-38] xicom: Core access failed. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-initialize the hardware target. Use open_hw_target to re-register the hardware device.
ERROR: [Xicom 50-38] xicom: Core access failed. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-initialize the hardware target. Use open_hw_target to re-register the hardware device.
ERROR: [Xicom 50-38] xicom: Core access failed. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-initialize the hardware target. Use open_hw_target to re-register the hardware device.
ERROR: [Xicom 50-38] xicom: Core access failed. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-initialize the hardware target. Use open_hw_target to re-register the hardware device.
ERROR: [Xicom 50-38] xicom: Core access failed. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-initialize the hardware target. Use open_hw_target to re-register the hardware device.
ERROR: [Xicom 50-38] xicom: Core access failed. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-initialize the hardware target. Use open_hw_target to re-register the hardware device.
ERROR: [Xicom 50-38] xicom: Core access failed. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-initialize the hardware target. Use open_hw_target to re-register the hardware device.
ERROR: [Xicom 50-38] xicom: Core access failed. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-initialize the hardware target. Use open_hw_target to re-register the hardware device.
ERROR: [Xicom 50-38] xicom: Core access failed. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-initialize the hardware target. Use open_hw_target to re-register the hardware device.
ERROR: [Xicom 50-38] xicom: Core access failed. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-initialize the hardware target. Use open_hw_target to re-register the hardware device.
ERROR: [Xicom 50-38] xicom: Core access failed. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-initialize the hardware target. Use open_hw_target to re-register the hardware device.
ERROR: [Xicom 50-38] xicom: Core access failed. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-initialize the hardware target. Use open_hw_target to re-register the hardware device.
ERROR: [Xicom 50-38] xicom: Core access failed. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-initialize the hardware target. Use open_hw_target to re-register the hardware device.
ERROR: [Labtools 27-3175] Target jsn-DLC9-Port_#0002.Hub_#0001 is no longer available.
Please use disconnect_hw_server to close the current server connection. Check cable connectivity and that the target board is powered up.
Restart the hw_server application running on host localhost, port 3121 and then use connect_hw_server to re-establish connection to target.

Please help

--Huey
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0 drozwood90 over 9 years ago

Hi there,

That error means that you do not have a clock running your debug logic. The JTAG cannot communicate with whatever debug core you are trying to attach to.

What is your source clock that drives everything? Are you using a block design to draw out the schematic?

--Dan
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0 Former Member over 9 years ago in reply to drozwood90

Hi Dan

Please help.
I instantiated the GTX 10GBASE-R example design to the processing wrapper. I am using the FCLK_CLK0 with 60Mhz in PS only for getting the clocks required for GTX: INIT_CLOCK_P and DRP_CLK_IN. And my top module like this:
################################################################
`timescale 1 ps / 1 ps

module design_1_wrapper
   (Q0_CLK1_GTREFCLK_PAD_N_IN,
    Q0_CLK1_GTREFCLK_PAD_P_IN,
    TRACK_DATA_OUT,
    RXN_IN,
    RXP_IN,
    TXN_OUT,
    TXP_OUT,
    DDR_addr,
    DDR_ba,
    DDR_cas_n,
    DDR_ck_n,
    DDR_ck_p,
    DDR_cke,
    DDR_cs_n,
    DDR_dm,
    DDR_dq,
    DDR_dqs_n,
    DDR_dqs_p,
    DDR_odt,
    DDR_ras_n,
    DDR_reset_n,
    DDR_we_n,
    FCLK_CLK0,
    FIXED_IO_ddr_vrn,
    FIXED_IO_ddr_vrp,
    FIXED_IO_mio,
    FIXED_IO_ps_clk,
    FIXED_IO_ps_porb,
    FIXED_IO_ps_srstb);
    input   Q0_CLK1_GTREFCLK_PAD_N_IN;
    input   Q0_CLK1_GTREFCLK_PAD_P_IN;
    (*mark_debug = "TRUE" *)output TRACK_DATA_OUT;
    input   [3:0]   RXN_IN;
    input   [3:0]   RXP_IN;
    output [3:0]   TXN_OUT;
    output [3:0]   TXP_OUT;
    inout [14:0]DDR_addr;
    inout [2:0]DDR_ba;
    inout DDR_cas_n;
    inout DDR_ck_n;
    inout DDR_ck_p;
    inout DDR_cke;
    inout DDR_cs_n;
    inout [3:0]DDR_dm;
    inout [31:0]DDR_dq;
    inout [3:0]DDR_dqs_n;
    inout [3:0]DDR_dqs_p;
    inout DDR_odt;
    inout DDR_ras_n;
    inout DDR_reset_n;
    inout DDR_we_n;
    output FCLK_CLK0;
    inout FIXED_IO_ddr_vrn;
    inout FIXED_IO_ddr_vrp;
    inout [53:0]FIXED_IO_mio;
    inout FIXED_IO_ps_clk;
    inout FIXED_IO_ps_porb;
    inout FIXED_IO_ps_srstb;

    wire   Q0_CLK1_GTREFCLK_PAD_N_IN;
    wire   Q0_CLK1_GTREFCLK_PAD_P_IN;
    wire TRACK_DATA_OUT;
    wire   [3:0]   RXN_IN;
    wire   [3:0]   RXP_IN;
    wire [3:0]   TXN_OUT;
    wire [3:0]   TXP_OUT;
    wire [14:0]DDR_addr;
    wire [2:0]DDR_ba;
    wire DDR_cas_n;
    wire DDR_ck_n;
    wire DDR_ck_p;
    wire DDR_cke;
    wire DDR_cs_n;
    wire [3:0]DDR_dm;
    wire [31:0]DDR_dq;
    wire [3:0]DDR_dqs_n;
    wire [3:0]DDR_dqs_p;
    wire DDR_odt;
    wire DDR_ras_n;
    wire DDR_reset_n;
    wire DDR_we_n;
    wire FCLK_CLK0;
    wire FIXED_IO_ddr_vrn;
    wire FIXED_IO_ddr_vrp;
    wire [53:0]FIXED_IO_mio;
    wire FIXED_IO_ps_clk;
    wire FIXED_IO_ps_porb;
    wire FIXED_IO_ps_srstb;

design_1 design_1_i
       (.DDR_addr(DDR_addr),
        .DDR_ba(DDR_ba),
        .DDR_cas_n(DDR_cas_n),
        .DDR_ck_n(DDR_ck_n),
        .DDR_ck_p(DDR_ck_p),
        .DDR_cke(DDR_cke),
        .DDR_cs_n(DDR_cs_n),
        .DDR_dm(DDR_dm),
        .DDR_dq(DDR_dq),
        .DDR_dqs_n(DDR_dqs_n),
        .DDR_dqs_p(DDR_dqs_p),
        .DDR_odt(DDR_odt),
        .DDR_ras_n(DDR_ras_n),
        .DDR_reset_n(DDR_reset_n),
        .DDR_we_n(DDR_we_n),
        .FCLK_CLK0(FCLK_CLK0),
        .FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
        .FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
        .FIXED_IO_mio(FIXED_IO_mio),
        .FIXED_IO_ps_clk(FIXED_IO_ps_clk),
        .FIXED_IO_ps_porb(FIXED_IO_ps_porb),
        .FIXED_IO_ps_srstb(FIXED_IO_ps_srstb));

    gtwizard_0_exdes gtwizard0exdes
        (
            .Q0_CLK1_GTREFCLK_PAD_N_IN(Q0_CLK1_GTREFCLK_PAD_N_IN),
            .Q0_CLK1_GTREFCLK_PAD_P_IN(Q0_CLK1_GTREFCLK_PAD_P_IN),
            .DRP_CLK_IN_P(FCLK_CLK0),
            .DRP_CLK_IN_N(FCLK_CLK0),
            .TRACK_DATA_OUT(TRACK_DATA_OUT),
            .RXN_IN(RXN_IN),
            .RXP_IN(RXP_IN),
            .TXN_OUT(TXN_OUT),
            .TXP_OUT(TXP_OUT)
        );
endmodule
###############################################

I got the errors during DRC:
Implementation
Place Design
[DRC 23-20] Rule violation (REQP-61) ibufds_connects_I_active - IBUFDS gtwizard0exdes/IBUFDS_DRP_CLK pin I has an invalid driver design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG

[DRC 23-20] Rule violation (REQP-62) ibufds_connects_IB_active - IBUFDS gtwizard0exdes/IBUFDS_DRP_CLK pin IB has an invalid driver design_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG

[Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.

Thanks.
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0 drozwood90 over 9 years ago

Hi there,

Could you tell me what clock drives your logic? Pasting your port definition is not really useful as we need to determine what clock drives the logic.

You said you are using a 60MHz clock that feeds the PS. What clocks have you brought out to the PL? What is FCLK_CLK0 configured as? Since that appears to be the clock needed for your entities, what is it connected to? You need to explicitly define those as well as the connection between. It is rather easy to do in the Block Design wizard to create the clock. Then you would need to define that clock in the XDC for use with your code. Lastly, actually connect the wire for that clock to the port input that you need it to be attached to. Have you done that?

--Dan
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