Dear All,
I am making a carrier board for the Picozed, and I was wondering if it is possible to swap pairs for the ethernet lines (not polarity swapping, but pairs e.g. 3<=>4)
Thank you all,
Peter
Dear All,
I am making a carrier board for the Picozed, and I was wondering if it is possible to swap pairs for the ethernet lines (not polarity swapping, but pairs e.g. 3<=>4)
Thank you all,
Peter
Hi Peter,
By default for the Vivado hw platforms that Avnet provides for the PicoZed the signals for the Ethernet interface are connected to the Processing System (PS) inside the Zynq device and their locations are thus fixed on the MIO pins on the device. It isn't possible to swap them.
However, since you are creating a custom carrier, you may be able to modify or create your own PicoZed design in Vivado to change the Ethernet interface from MIO to EMIO. Putting the interface on EMIO will route the Ethernet MAC signals to PL I/Os, thus giving you greater control over how they are arranged on the device I/Os and across the carrier PCB routed to the Ethernet PHY. Keep in mind, though, that the Ethernet interface is RGMII when on MIO and GMII when on EMIO. This means the Ethernet interface uses a lot more pins when on EMIO. The Xilinx Zynq TRM (UG585, Ch. 16) has more information.
https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
--Tom
Hi Peter,
By default for the Vivado hw platforms that Avnet provides for the PicoZed the signals for the Ethernet interface are connected to the Processing System (PS) inside the Zynq device and their locations are thus fixed on the MIO pins on the device. It isn't possible to swap them.
However, since you are creating a custom carrier, you may be able to modify or create your own PicoZed design in Vivado to change the Ethernet interface from MIO to EMIO. Putting the interface on EMIO will route the Ethernet MAC signals to PL I/Os, thus giving you greater control over how they are arranged on the device I/Os and across the carrier PCB routed to the Ethernet PHY. Keep in mind, though, that the Ethernet interface is RGMII when on MIO and GMII when on EMIO. This means the Ethernet interface uses a lot more pins when on EMIO. The Xilinx Zynq TRM (UG585, Ch. 16) has more information.
https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
--Tom
Hi Tom,
Thanks for your answer. However, I am not going to connect a different MAC but using the same as already on the Picozed - I am wondering if everything will still work if I swap a pair between the my ETH connector with integrated magnetics and the connector of the PicoZed.
Best,
Peter
By the way, I just found this information:
Table 116 on page 111 where it seems possible - could you please check with the HW team?
Thank you
Since you don't plan to change the Zynq PS Ethernet MAC to use EMIO instead of the MIO, then I am afraid what you want to do - swap a pair of signals between the ETH connector and PicoZed connector - won't be possible.
--Tom
Upon further review I was just chatting with a colleague who suggested this swapping might be possible within the Ethernet PHY. If this is the case this could be done via register writes over the MDIO interface. This would require custom software running on the PicoZed at boot to init the register. The Marvell datasheet will have more information:
--Tom
The Hardware team agrees that it might be possible, but we've never done it, and we aren't the authority on Marvell PHY operation. Proceed at your own risk. You may want to consult with your local Marvell FAE to get their input on the matter.
--Tom