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PicoZED Carrier V2 USB UART Boot from flash

amkichu

I have a basic design with DRAM and UART1 configured in PS and PL LEDs with pattern Ah.  -> OK

Zynq FSBL + Zynq DRAM tests application project in SDK --> OK

Created BOOT.mcs (fsbl.elf, system.bit, dram_test.elf) -> OK

Programmed the BOOT.mcs into flash -> OK

CP210x_Windows_Drivers.zip installation from https://www.silabs.com/developers/usb-to-uart-bridge-vcp-drivers -->OK

COM port and Baudrate settings at Teraterm with 115200 --> OK

UART display on Teraterm for DRAM memory test using dram_test.elf over JTAG -->OK

UART display on Teraterm for DRAM memory test when boot from flash --> NOK

COM port and Baudrate settings at Teraterm with 115200 --> OK

FPGA DONE LED --> OK

Orange LED at J1 --> OK

 

Complaint is UART display on Teraterm for DRAM memory test when boot from flash --> NOK

  • I remember looking at this a long time ago. My memory is hazy, so forgive me if I'm off track. From what I recall, the problem with booting the DRAM test in particular from Flash is that the FSBL and DRAM app overwrite each other. When you download over JTAG, you are using a TCL script for FSBL, not a flash-stored FSBL. From what I remember, in order to test the memory, the DRAM app runs from internal memory so you don't trash the app when the destructive testing runs through the memory. However, the FSBL also targets the internal memory, so you have a conflict. If you try booting any other test application from Flash (like Hello World or Peripheral Tests), then it will work. To get the DRAM test to work from Flash, you will have to manipulate the linker scripts for both App and FSBL and edit the range for which the application tests.

    Bryan