XC7Z010 not able to bootup with DDR3L ( MT41K256M16TW-107 AUT:P) operating frequency of 533MHz

Is this a custom board or a SOM?  I'm assuming a custom board.

1. Have you correctly set the trace lengths for the DDR in Vivado?

2. Have you tested the DDR signal integrity?

It really sounds like you have a signal integrity issue.  Maybe termination not correct?

Hi dyessgg ,

please find the signal integrity waveforms for clock and data,

Clock : Simulated with 800MHz

Termination resistors we used for single ended was 40.2 Ohm and for Clock used 80.4 Ohm. 

Let me know if you need any more inputs. 

Janakiram 

These look WAY too clean for a real board.  The line "Clock : Simulated with 800MHz".  Is this actual captures from your board or some simulation?

I'm not an expert, but the terminations look good to me.

Are your trace lengths matched within tolerances?  Have you entered those trace lengths into Vivado to generate the startup configuration code?

Are there discontinuities loo too many vias or crossing different ground planes?

I recall a (long time ago) a board had weird DDR issues and it turned out the board was not being fed enough power.  A voltmeter could not capture the dips in voltage but a scope did.  Maybe check the power with a scope triggered at a very slight voltage drop.  Check all supplies related to the DDR.

Beyond that, you're getting into the deep magic of DDR I tend to stay clear of.

These look WAY too clean for a real board.  The line "Clock : Simulated with 800MHz".  Is this actual captures from your board or some simulation?

I'm not an expert, but the terminations look good to me.

Are your trace lengths matched within tolerances?  Have you entered those trace lengths into Vivado to generate the startup configuration code?

Are there discontinuities loo too many vias or crossing different ground planes?

I recall a (long time ago) a board had weird DDR issues and it turned out the board was not being fed enough power.  A voltmeter could not capture the dips in voltage but a scope did.  Maybe check the power with a scope triggered at a very slight voltage drop.  Check all supplies related to the DDR.

Beyond that, you're getting into the deep magic of DDR I tend to stay clear of.

Hi dyessgg ,

Continuing with what JANAKIRAM12137 shared.
We are using DDR3L MT41K256M16TW-107 AUT:P. The closet chip that is available on vivado is MT41K256M16 RE-125.
[The Picozed board also has this same ddr IC and they used this exact configuration on vivado
Our custom design is based on picozed eval board and it too has two DDR3L.]

DDR controller configuation:- 
Same as Picozed


Memory Part Configuration:-
Kept it same as Picozed board.


Training Board details:-
This details are filled based on the track lengths of our custom board (pls find the attached signals file that has the routing related values)

With this configuration values put in , I have seen the following observations:-
1.At 303MHz : All the DDR tests are passing. The board boots up without any misbehavior.
2.At 333MHz: The DDR test fails for 1024MB of data. The board booting is inconsistent
3.At 400MHz: The DDR test fails for 256MB,512MB,1024MB. Board hardly boots
4.At 533.3333333MHz : All the DDR tests fail.

I have tried keeping the delay values exactly like the eval board, but again the behavior is same.

Can you please share you insights based on these observations.

Regards,
Sameeksh Shetty

I don't see anything obviously wrong.  I would scope all of your power rails dealing with the DDR and trigger on any voltage dips.  

It still sounds to me like a signal integrity issue.  You didn't answer the question about the eye diagrams being actual or simulated.  If simulated, make sure to capture real traces at the various frequency nodes you mentioned to see what is different.

You're going beyond my experience now. 

hi dyessgg above images was belongs to simulation. will provide the actual hardware waveforms and voltage dips observations as well. Thanks for your guidance. 

Janakiram 

If you can share the layout of the DDR3L it might help us deduce what needs to change.

Hi i am not able to share the  PCB file but i can share my images, if my PC issues resolved i can upload the file by tomorrow.

BANK 0 Routing lengths,

BANK 1 Routing lengths,

BANK 2 Routing lengths,

BANK 3 Routing lengths,

ADDR_CMD_CLK Routing Lengths,

Let me know if you need any more information.

Thanks in advance. 

Janakiram  

A quick inspection looks like the data is correct, but double check the trace lengths and timings, just in case.

Assuming the trace lengths are programmed properly into Vivado and the trace impedance and terminations are correct, the only thing I can think of is: have you regenerated your entire software stack with the new values generated by vivado. You can't use any firmware from the demo board.

I personally haven't done this with Vivado yet, but with competitor tools, I had to generate a new u-boot and flash it onto the boot device to ensure that the timings were loaded properly on boot up before the DRAM training begins.

Here's a dumb question, just in case: are you sure you have the right speed parts installed on the board? Double check that part number and speed grade.

Hi brianmckee ,

Thanks for the valuable inputs.

we have cross checked the Trace lengths all are same as provided in the above, impedances we have maintained as suggested by the Xilinx for DDR3L ( 40Ohm and 80Ohm). 

As per your suggestion we are going through the timings will update you soon. 

Thanks for the support. 

Janakiram 

If you can't find any major mistakes in the data you entered into the tool, I can only think of little things to check, which shouldn't really affect 533 MHz.

For example, the wiggles should use smooth curves, not angles and there should be a complete and solid ground under all traces to and from the DDR3.

One other thing to try, check the dram timing provided by Xilinx in the tool against the specification for the exact 1066 DDR3 part you are using.

Make sure the CAS latency and other timings are in bounds. Make sure you aren't using numbers that are too large because you are running half the clock rate of the DDR. I'm thinking about refresh and other timings that matter for volatile memory.

If you still can't get it to run at speed, try delaying the critical timings by one clock just to see if you can get it to work. Then pull back the timings one at a time until it doesn't work. That will at least give you some idea what signal to look at with a scope.

Also, check your termination resistors, is it possible they were populated with the wrong values?

Have you looked at clock, ras, cas, we and a0 at the load to see what they look like? You need to check the eye pattern and make sure there isn't some errant ringing. Looking at the data eye patter should show no issue, unless there's a really bad impedance miscalculation.