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Driving external clock to AD9361 (improper termination?)

Former Member

Hi,

 

I'm making a custom carrier for the PicoZed SDR, which will connect an external clock to the AD9361.  Looking at the clock input circuit in the SOM schematics (pg. 8), I'm unsure what the proper way is to drive this.  The AD9361 datasheet says it wants a max 1.3Vpp clock, AC coupled.  It looks like when using the internal oscillator, it uses a capacitive divider with a series 18pF and using the ~7pF "on" capacitance of the switch and the ~10pF capacitance of the AD9361 input to drop the 1.8V oscillator down to ~0.9Vpp.

 

But for the external input, there's a 50 ohm termination resistor, and no AC coupling capacitor after it.  How do you recommend driving this?  Should that resistor (R5) be removed, and use a capacitive divider for my external clock?  If I provide an AC coupled signal that can drive 50 ohms, I believe the signal will be clipped by swinging below the rail of the switch (U5), and the resistor will also provide a 50 ohm DC path to ground from the XTALN input.

 

I also see that the development kit terminates at the SMA with 50 ohms and no AC coupling capacitor... which is essentially in parallel with the existing 50 ohms, making the clock input 25 ohm terminated when mated to the development kit.

 

Am I missing something, or is this an error that should be changed on a future rev?  And if so, what change would you expect to make?  Of course I'd like to design my carrier to be compatible with future revs without requiring additional modifications.

 

Thanks,
Pat

  • 0

    Hi Pat,

    We're having a look at this right now. I think you may have found an oversight in the carrier design.  I'll get back to you later today or Monday.

     

    Thanks,

    Matt

  • 0

    Hi Pat,

    We missed this during the prototype stage because we were injecting a clock from external equipment, which is already cap coupled.

    We will add the series AC cap to Rev D of the SOM, which is in layout right now.

    For your custom carrier, I would suggest adding a series cap for prototyping with Rev C and earlier SOMs that do not have it on the module. For production with Rev D SOMs, make a BOM change to a zero ohm resistor on your carrier.

     

    Thanks for catching this and sorry for any inconvenience this causes you.

    /Matt

  • 0

    Hi Matt,

     

    Thanks for the info.  Just to clarify, Rev D will have the series capacitor like this: http://imgur.com/XYt3wb9 ?  When do you expect the Rev D SOM will be released?

     

    You mention running the Rev C and earlier from an AC coupled clock, but I'm not sure that'll perform well.  Correct me if I'm wrong, but if you AC couple before the 50 ohm resistor, our 1.3Vpp clock will swing between -0.65V and +0.65V relative to GND.  When it goes through the switch, the bottom half of the waveform will be clipped, as the switch is only good from 0V - 3.3V.  Though with a square wave, the clipped signal may not be too much of a problem.

     

    But, the main problem I see is with the DC coupling of the XTALN input.  My assumption is that the clock input of the AD9361 is basically set up like a Pierce oscillator.  That is, an inverter with a large feedback resistor to bias it in the linear region (near Vdd/2).  With a 50 ohm DC path to GND connected to the XTALN pin, it's going to overpower the feedback resistor, essentially dragging the input down to 0V, rather than sitting at Vdd/2.  And our clock signal now goes from 0V - 0.65V, never going above Vdd/2... so the inverter may never "switch" (or it may switch on the ringing at the top of the signal).  And of course it's worse if our original clock was less than 1.3Vpp.

     

    Wouldn't it be better to drive it DC coupled (i.e. 3.3V clock through a 82 ohm resistor, into the existing 50 ohms)?  This isn't ideal as it still renders the feedback resistor useless, so our clock isn't exactly symmetric around the switching threshold, but I think as long as we keep it close to 0V - 1.3V, it should be better than AC coupling from the carrier board.  And I believe the same circuit would "just work" with a Rev D SOM.

     

    Thoughts?

     

    Thanks,

    Pat

  • 0 in reply to Former Member

    Pat:

    www.analog.com/ad9361

    From the latest datasheet (Rev E):

    Page 19 : Reference Frequency Crystal Connections. When a crystal is used, connect it between these two pins. When an external clock source is used, connect it to XTALN and leave XTALP unconnected.

     

    From the most recent user guide:

    http://www.analog.com/media/en/technical-documentation/user-guides/AD9361_Reference_Manual_UG-570.pdf

    Page 15: an external reference clock needs to be ac-coupled to XTALN (Pin M12). XTALP (Pin M11) is not connected (leave floating)

    ---

    So, no - it can not be DC coupled (at least from the AD9361's perspective). The 50 ohm should come out - that really only works if things are being driven by test instrumentation (which is how it was verified). Most low cost oscillators can not drive a 50 ohm load, so we shouldn't have done it this way...

    The "near Vdd/2" is the issue - any DC offset (no matter how small) has the possibility of causing jitter, which most people aren't going to like as things get multiplied up by the RF PLLs.

    The short answer is - you found a bug. We are digging into the correct way to fix it. I need to talk to someone who is out today, but will be back tomorrow, and then we should have a definitive answer. 

    Sorry for the delay.

    -Robin

  • 0 in reply to rgetz

    Thanks... yeah, I had given it some more thought and decided that I'd be removing the 50 ohm termination on my SOMs (so if you remove it from Rev. D, I won't miss it).  Since I'm using the SOM as part of a standalone embedded system (with its own oscillator), it didn't seem worth the extra power or real estate for the circuitry to drive the clock into 50 ohms.

     

    Thanks,

    Pat

  • 0

    I saw this diagram was posted the other day: https://wiki.analog.com/resources/eval/user-guides/pzsdr/carriers/fmc .  Can you confirm that this is how the circuit will look on Rev D?  With 18pF after the switch, I assume that means the external clock should be approximately 2Vp-p max (capacitive divider of 18pF and internal 10pF)?

    Thanks,
    Pat

  • 0

    Hi Pat,

    Yes, that's a screen grab of the Rev D schematic.

    Thanks

    Matt

  • 0

    hi Matt,

     

    From the diagram, when IO_00_34_AD9361_CLKSEL is high, the external clock is selected but Y4 will also be enabled. Is this interpretation correct?

    Thanks!

    Tan

  • 0 in reply to Former Member

    Hi Tan:

    When IO_00_34_AD9361_CLKSEL is high, the 40MHz osc (Y4) is enabled; so is the MOSFET (Q6) which inverts the logic to the analog mux (U5) select pin IN1. This disables the S1A input and selects S1B which is connected to Y4.

     

    /Matt

  • 0 in reply to mbrown

    In picozed sdr kit I am getting 40 MHz output clock at y4 output. Is io_00_34__ad9361_clksel default value is high? How fpga is giving high at this pin?  How  can I configure clock out from ad9361 to fpga?