DAC sampling frequency over 7 Gsps with ZCU208

Hi McG,

This is reproducible through the HDL Coder Workflow advisor which is the correct place to set the options and sampling rates.  The ZCU208 HDL Coder support package functionality is split across some Avnet owned code and MathWorks.  MathWorks does not install all of the source code for these tools, some of it is p-code.  The error for the sampling rate seems to be somewhere in the shared MathWorks RFSoC support package, the function that sets the PLL does not seem to be getting the selected DUC Mode.  I will update again if there is a short term way to work around this.  An official release that fixes it will take a little time to work through the release processes.

Thanks for reaching out

Hi lightcollector,

many thanks for your answer. So, at the moment I cannot use the DACs beyond 7 GHz... Anyway, I noticed that the same issue is generated for ZCU216, this means that the problem is actually related to the RFSoC support package. I opened a ticket on the Matlab support website and I'll keep you posted if I have news.

Regards

Hi,  Yes it seems to me that there is a shared MathWorks component that is not getting the DUC mode setting, they have some 208 and 216 functionality mixed in with 111 in some modules.  I don't even have the source for some of the modules but can indirectly get access and am awaiting a response from MathWorks.

Good that you posted a ticket too.  I have a direct line to the right people at MathWorks and I am taking care of the ZCU208 HDL Coder tools overall.  So you are conversing with the right person.  The answer for the short term may not be pleasant but I will let you know what is going on.

Hi McG,

Still a work in progress but wanted to pass along some status.  At least part of the issue is now understood and can be worked around by modifying source code in a section of MathWorks RFSoC add-on.  With some changes I can generate Vivado projects now using the HDL Coder Workflow Advisor for the ZCU208. However, the resulting Vivado hardware design still does not compile with just that fix.  Once I have a more complete solution I will pass it along.  It might be a few days or more before I reply again.

Kind regards

Hello lightcollector,

I don't have good news from matworks. There is a guy of UK support team which is working on the problem but he isn't still able to solve it.

I'll keep you posted!

Regards

Hi McG,

The good news is I believe I understand at all levels now as to why when choosing IMR mode and Fs > 7GHz it does not work.

The bad news is that it involves multiple levels of components all the way down to the way Vivado interacts with the RF Data Converter IP properties.  There is no way I can concisely explain the precise details of what is going on in this format.  The changes need to occur mainly in the MathWorks owned components, some of the changes are universal for both the ZCU216 & ZCU208.

There is a MathWorks process to follow to get the changes integrated, tested and then distributed to you and other customers.  I cannot speak directly for MathWorks as to their timeline or how this will get resolved.  I can assure you that I am doing everything I can to provide the technical details and work toward a resolution but I cannot promise or insinuate any timeline as to when or how it will be released.

It might be a while until I reply to this thread again but that doesn't mean it is forgotten or not being worked on.

Kind regards

Hi McG,

The good news is I believe I understand at all levels now as to why when choosing IMR mode and Fs > 7GHz it does not work.

The bad news is that it involves multiple levels of components all the way down to the way Vivado interacts with the RF Data Converter IP properties.  There is no way I can concisely explain the precise details of what is going on in this format.  The changes need to occur mainly in the MathWorks owned components, some of the changes are universal for both the ZCU216 & ZCU208.

There is a MathWorks process to follow to get the changes integrated, tested and then distributed to you and other customers.  I cannot speak directly for MathWorks as to their timeline or how this will get resolved.  I can assure you that I am doing everything I can to provide the technical details and work toward a resolution but I cannot promise or insinuate any timeline as to when or how it will be released.

It might be a while until I reply to this thread again but that doesn't mean it is forgotten or not being worked on.

Kind regards

Hi McG,

MathWorks has offered a direct email for you to reach out to help with this.  Please use 'fpga_expert' as an email contact using the mathworks.com domain.  A real human that we are working with on HDL Coder for the Xilinx RFSoC eval boards will respond :-)

Kind regards

Hi lighcollector,

thank you very much for your replays. I really appreciate it... Unfortunately at the moment I'm totally stuck with my work, I hope the problem will be solved asap.

So can I send an email to fpga_expert?

Regards

Yes, please reach out with an email to 'fpga_expert' at the mathworks.com domain, less the quotes of course.  They want to know who in the UK you are working with so we can make sure it gets officially resolved.