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CLK104 PLL Lock

dchien

The CLK104 clock board on my ZCU208 evaluation board does not have all PLL lock LEDs on. The clock distribution PLL (U2) has its lock LED (DS1) on, but the DAC PLL (U7) has its LED (DS3) off and the ADC PLL (U5) has its lock LED (DS2) off. Do I have a defective CLK104 board? What can cause the ADC and DAC PLLs not locking (LEDs off)?

Thanks!image

  • Hi,

    The clock 104 board is programmable using PS oriented software.  Can you please clarify which software you are running on the zcu208 and, or, what remote control PC program to configure the zcu208?  And also please, what are you trying to have the clk104 do?

    Thank you

  • What I recall is that the ADC/DAC PLL lock LEDs only turn on when you have configured the LMX devices to synthesize a sample rate clock (the AMD doc UG1437 refers to them as RF PLLs). In this scenario you need to cable the RF PLL outputs from the CLK104 to the zcu208.

    However, if you are using CLK104 to deliver a reference clock to the RFDC internall PLLs (ex: 245.76MHz), these connections are made through the RFMC2.0 connector. This is the default configuration of CLk104 for Avnet RFSoC Explorer. In this scenario only the LMK LED lock will activate as the LMX PLLs are not used.

    My board is being used by a colleague this week, but I can confirm early next week.

  • in reply to lightcollector

    I am using https://github.com/AvnetDev/hdlcoder-zcu208-zip/releases/tag/v1.03 SD image with MATLAB HDL Coder design flow to implement signal processing with ADC running at 2GSPS and DAC running at 6GSPS. Thannks.

  • in reply to mbrown

    In my setup, the outputs of the ADC RFCLK from CLK104 are connected to ZCU208 ADC CLK inputs and outputs of the DAC RFCLK from CLK104 are connected to ZCU208 DAC CLK inputs. When ADC and DAC are used in the design, I believe both LMX2594 PLL lock LEDs should be on. Please verify the LED status when you get your board back next week. Thanks.

  • in reply to dchien

    Hi, That tool does not provide any direct way to re-program the CLK104. So do you have a need to reprogram the CLK104 or are you just trying to use the defaults here?  And are you just trying to rearrange the clock distirbution internally using the options that HDL Coder provides?

    One tip I can offer is that if you have generated the Vivado project using HDL Coder, you can open the design directly in Vivado and inspect the RF Data Converter IP.  Specifically inspect the clock distribution properties tab to make sure it is happy with the settings you selected.

    A sort of funny thing here is that mbrown had my board to start with, so I don't have a board either to double check the LEDs at this time.  Sorry about that, just wanted to clear that up as to why I can't firsthand verify your direct question.

    Understanding your intentions about what you are trying to accomplish with the system clock distribution would help provide better guidance or alternative solutions.

    We do work with MathWorks and I believe we will be having a direct meeting sometime soon.  If you want to converse directly before that, you can send an email to: rfinfo @ Avnet DOT com  mention you want to speak with LightCollector and the person that manages that email will forward me your email and we can converse directly if you would like.

    Thanks

  • in reply to lightcollector

    Hi, I am using the default clock configuration from the HDL Coder design flow within MATLAB. I had a working ZCU208 setup also and did not pay attention to the two ADC/DAC PLL lock LED status at the time. I am working on a second setup and the first setup is not with me anymore. I am experiencing issues with my design that works at lower IF but fails at higher IF. Then I notice the PLL lock LEDs not on. Thanks.

  • in reply to dchien

    Ha, none of us seem to be able to hang onto our zcu208 boards :-)

    Would have to have more details to determine why a higher IF mixer frequency is impacting your progress.  There are many reasons why higher IF frequencies could have issues.  Not sure what your system level understanding is, but one possible explanation is that without IMR DAC mode turned on, 2 images come out the DAC.  If you don't have proper low or bandpass filtering in the analog domain, it can result in aliasing in your ADC samples.  Again, if you want to have a more detailed discussion reach out to the address I sent.

  • in reply to lightcollector

    I have a bandpass filter on the IF input to the ADC. The high and low IF issue is on the input ADC side. I sent an email to the address you specified at 1:21pm Pacific. Hope to connect with you soon. Thanks.