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RFSoC ZCU 208 whit Matlab HDL Coder - Getting Startet trouble

rcarli

Hi there.

I went through the "Getting Started with HDL Coder for the Xilinx ZCU208 RFSoC Gen 3 development board" (rfsoc-hdlcoder.readthedocs.io/.../zcu208.html) to test and familiarize myself with the functionality.

It worked fine up to step 12. But at the HDL Worklow Advisor at "4.2 Generate Software Interface" it gets stuck. This is because the SoC Blockset Toolbox is required. Do I really need this toolbox, is this a new requirement, or is something else wrong?
According to the "Getting Started ... - Required Software" section, there is no need.

I also get further warnings and notes that something cannot be generated and should be changed manual, is this possibly due to the version difference between the creation of the model and my version? Or can i ignore them?

I am using:

  • Xilinx ZCU208 RFSoC Gen 3
  • Matlab 2023b
  • Vivado 2020.2
  • Avnet RFSoC Explorer 3.0.0
  • Fixed Point Designer Toolbox v. 23.2
  • HDL Coder v. 23.2.0
  • HDL Coder Support Package (FPGA Boards, RFSoCDevices, Zynq Platform) v. 23.2.0
  • DSP System Toolbox v.23.2
  • The unchanged Simulink Model out of the example folder -> rfsocADCCapture

Thank you in advance and best regards

  • 0

    Hi, You can uncheck the box in step 4.2 and you should be good to go! In spite of what it says you don't need SoC Blockset.

    image

    I am working on updating the instructions, each version of MathWorks tools brings a new challenge! R2024a required updating the example files ot R2024a (but the original versions are also included).  R2024a is now supported but you will officially have to install the latest version of RFSoC Explorer to get the updated plug-in for this as well.  If you do go the R2024a route MathWorks has a new support package for RFSoC and you have to run the ZCU216 board setup and must select to install libiio.

    I will post here again shortly after I make the new instructions go live.

    Thanks for your patience.

  • 0 in reply to lightcollector

    Hi,

    The instructions and examples for R2024a are now live at https://rfsoc-hdlcoder.readthedocs.io   In your case, if you were able to figure out how to proceed I would stick with R2023a if you have it working.  Otherwise, you would have to reinstall everything again for R2024a.  For ZCU208 HDLC not much has really changed from a feature perspective in R2024a vs R2023b.  Both also use Vivado 2020.2 as well.

    Kind regards

  • 0

    Hi, I replied in your other thread about the waveform issue.  At the time of the prior reply, the change MathWorks made with the way the HDLC for zcu208 plugin operates (delivered with RFSoC Explorer 3.1) was unknown then to no longer work with R2023b.

    The instructions were updated recently to point this out.  The intent is to change the next release of RFSoC explorer to install the prior plugin (delivered with RFSoC Exp 3.0) revision for R2023b and for R2024a install the version that is currently installed by RFSoC Explorer 3.1.  I do not know when the next version of RFSoC Explorer will be released to fix this.

    If you are being inhibited until it is fixed, let us know.  I can provide a way to manually force installing the hdl coder plugin for zcu208.