Hi there.
I went through the "Getting Started with HDL Coder for the Xilinx ZCU208 RFSoC Gen 3 development board" (rfsoc-hdlcoder.readthedocs.io/.../zcu208.html) to test and familiarize myself with the functionality.
It worked fine up to step 12. But at the HDL Worklow Advisor at "4.2 Generate Software Interface" it gets stuck. This is because the SoC Blockset Toolbox is required. Do I really need this toolbox, is this a new requirement, or is something else wrong?
According to the "Getting Started ... - Required Software" section, there is no need.
I also get further warnings and notes that something cannot be generated and should be changed manual, is this possibly due to the version difference between the creation of the model and my version? Or can i ignore them?
I am using:
- Xilinx ZCU208 RFSoC Gen 3
- Matlab 2023b
- Vivado 2020.2
- Avnet RFSoC Explorer 3.0.0
- Fixed Point Designer Toolbox v. 23.2
- HDL Coder v. 23.2.0
- HDL Coder Support Package (FPGA Boards, RFSoCDevices, Zynq Platform) v. 23.2.0
- DSP System Toolbox v.23.2
- The unchanged Simulink Model out of the example folder -> rfsocADCCapture
Thank you in advance and best regards
