How to enable both DDR4s on ZCU208 RFSoC Simulink models where I like to have both ADC and DACs streaming to/from separate DDR4?

I also modified the add_system.tcl as below:

if {[string first "zcu208" $BOARD_PART ]!=-1} {
# Create instance: ddr4_0, and set properties
set ddr4_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0 ]
set_property -dict [ list \
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} \
CONFIG.C0.CS_WIDTH {2} \
CONFIG.C0.DDR4_AxiAddressWidth {32} \
CONFIG.C0.DDR4_AxiDataWidth {256} \
CONFIG.C0.DDR4_CLKOUT0_DIVIDE {3} \
CONFIG.C0.DDR4_Clamshell {true} \
CONFIG.C0.DDR4_DataWidth {32} \
CONFIG.C0.DDR4_InputClockPeriod {3334} \
CONFIG.C0.DDR4_MemoryPart {MT40A1G8WE-075E} \
CONFIG.C0_CLOCK_BOARD_INTERFACE {default_sysclk_c0_300mhz} \
CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram_c0} \
CONFIG.RESET_BOARD_INTERFACE {reset} \
] $ddr4_0

puts "DDR4 block: $ddr4_0"

# Create instance: ddr4_1, and set properties
set ddr4_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_1 ]
set_property -dict [ list \
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} \
CONFIG.C0.CS_WIDTH {2} \
CONFIG.C0.DDR4_AxiAddressWidth {32} \
CONFIG.C0.DDR4_AxiDataWidth {256} \
CONFIG.C0.DDR4_CLKOUT0_DIVIDE {3} \
CONFIG.C0.DDR4_Clamshell {true} \
CONFIG.C0.DDR4_DataWidth {32} \
CONFIG.C0.DDR4_InputClockPeriod {3334} \
CONFIG.C0.DDR4_MemoryPart {MT40A1G8WE-075E} \
CONFIG.C0_CLOCK_BOARD_INTERFACE {default_sysclk_c1_300mhz} \
CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram_c1} \
CONFIG.RESET_BOARD_INTERFACE {reset} \
] $ddr4_1

}

Hi, If you haven't already figured out what your issue is, there isn't enough here for me to pinpoint what is going on with respect to your unique system.

If any partial Vivado project is created, take a look at that from within Vivado itself.  If there isn't any Vivado project, then I recommend generating one with an example design that is closest to where you want to go.  Then take that design and modify it using purely Vivado to add the new functionality.  Then export the block design tcl and use it to double check your unique customization of the various .m and .tcl files.

If you have already done the above, then my guess would be that you haven't modified enough of the existing hard coded wiring that MathWorks HDL Coder for RFSoC creates.  One approach would be to add after HDL Coder for ZCU208 tcl does its' things, some tcl that deletes portions of the original design and then re-add and/or re-wire the old and new pieces to do what you want.  If you could do this in the plugin then you could continue to rely on your Simulink simulation.  But you could add your custom DDR purely through Vivado tcl scripts and for Simulink, add the memory external to the DUT; this would allow you to do some amount of simulation within Simulink still.

HDL Coder for RFSoC builds a fairly rigid platform around the users single clock domain DUT algorithm Simulink block.  This makes it easy for users to get started with the tradeoff that not all board features are usable or easy to use.

Keep us posted on your progress, thanks

Hi, thank you very much for the reply. Yes, I have modified the vivado project from other examples and added axi_interconnects and the 2nd MIG for the 2nd DDR4 interface. I also generated .tcl file within vivado. But the issue I have is connecting the Simulink to the modified .tcl files! It always overwrites what I do on .tcl files when I am creating the Vivado project under HDL workflow advisor. That's where I am stuck! I have modified the reference designs and plug-ins and everything works in Workflow advisor except where I get to creating the Vivado project! 

Hi, thank you very much for the reply. Yes, I have modified the vivado project from other examples and added axi_interconnects and the 2nd MIG for the 2nd DDR4 interface. I also generated .tcl file within vivado. But the issue I have is connecting the Simulink to the modified .tcl files! It always overwrites what I do on .tcl files when I am creating the Vivado project under HDL workflow advisor. That's where I am stuck! I have modified the reference designs and plug-ins and everything works in Workflow advisor except where I get to creating the Vivado project! 

Hi, there are various .m files and .tcl files that generate the Vivado block design.  The way MathWorks designed the tool, it is not intended that an end user modify their copyrighted files.  Most of the MathWorks tools, including this one are not open-source.  Officially I cannot condone or support modifying MathWorks tools: legally and liability-wise you are on your own to do such.

But... none of the source code that generates the .tcl code that wires up and configures the various IPs in the Vivado block design is hidden.  In addition to the ZCU208 specifics that are installed through RFSoC Explorer, MathWorks RFSoC Add-On for HDL Coder also installs various source code including a common part, as well as specifics for the ZCU111 and ZCU216 RFSoC dev boards.

Good luck!