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AXI in ZYNQ

Former Member

Hi,

I am doing interface between ps to pl in ZYNQ processor. I need some clarifications on interface.
1. what is the frequency of AXI4 clock frequency.
2. for interface have 3 ways like (GPIO, ACP), I need some technical document to use the methods in vivado 2014.1.

Thanks & Regards
Ashwak ali S.

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  • 0

    Hi,

       Thank you for your response. now my hardware implementation is completed for interface between PS to PL using vivado 2014.1.
    interface procedure:
    1. I am using Block RAM to send data.
    2. BRAM controller is send data to DMA.
    3. DMA send data to PS.
    now I need to debug the signals. so what is the procedure to debug the signals. and which signals are debug from processor side. if you have any related documents please forword to me.

    Thanks & Regards
    Ashwak ali S.

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  • 0

    Hi,

       Thank you for your response. now my hardware implementation is completed for interface between PS to PL using vivado 2014.1.
    interface procedure:
    1. I am using Block RAM to send data.
    2. BRAM controller is send data to DMA.
    3. DMA send data to PS.
    now I need to debug the signals. so what is the procedure to debug the signals. and which signals are debug from processor side. if you have any related documents please forword to me.

    Thanks & Regards
    Ashwak ali S.

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