AXI in ZYNQ

The frequency of the AXI clock in your design depends on your hardware implementation. The Zynq is a programmable device and you can set the AXI clock frequency based on your design as well as the maximums for your specific device and speed grade.

For the Zynq device on the ZedBoard and MicroZed the default clock rate defined using the Vivado tools will be 100 MHz.

You might want to take the time to run through some of the training material available. A good place to start would be the Avnet Zynq Speedway workshops:

Developing Zynq-7000 All Programmable SoC Software (Vivado 2013.3)

Developing Zynq-7000 All Programmable SoC Hardware (Vivado 2013.3)

which will give you a better idea of how the various interfaces work. Once you have generated a working Zynq hardware design in Vivado and 'exported' this design to the SDK you can open up the system.mss file. Here you will find links to example code for each of the available peripherals.

-Gary

Hi,

   Thank you for your response. now my hardware implementation is completed for interface between PS to PL using vivado 2014.1.
interface procedure:
1. I am using Block RAM to send data.
2. BRAM controller is send data to DMA.
3. DMA send data to PS.
now I need to debug the signals. so what is the procedure to debug the signals. and which signals are debug from processor side. if you have any related documents please forword to me.

Thanks & Regards
Ashwak ali S.

There is an example of using the Vivado Analyzer to debug PL logic in Lab 8 of the Zynq Hardware Speedway workshop mentioned above.

The Zynq Concepts, Tools and Techniques tutorial for Zedboard has a section on using the Vivado Analyzer: http://zedboard.org/support/design/1521/11

The Xilinx Vivado Design Suite tutorial on Programming and Debugging, UG936, also has details on using the Vivado Analyzer: http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug936-vivado-tutorial-programming-debugging.pdf

-Gary

Hi,


    I am doing interface between PS to PL in vivado 2014.1. I need to transfer data (write and read) between PS to PL.
    hardware implementation for PS to PL:
         Blocks:
            Block RAM
            Block RAM controller
            AXI interconnect
            ZYNQ processor
1. Implementing Block RAM for data transfer.i am using COE file in block RAM block.
2. Block Ram controller connect Block RAM and AXI interconnect.
3. AXI interconnect for PS to PL.

now I want to debug(data transfer) Block RAM and Block RAM controller.
I follow one procedure
  first use MARK DEBUG options for which one need to debug. i am using for BLOCK RAM and BLOCK RAM CONTROLLER
  run the synthesis
  create ILA file
  gemerate bit file
  export to SDK
  add signls to wave form
  run
but the signals shows all zeros. now have any document for debug or how to debug those blocks.


Thanks & Regads
Ashwak ali S.
 

Not sure why you would use a COE file unless it is just to initialized the BRAM contents. If you would like an example of a working design that implements an AXI Block RAM controller and a Block RAM and uses DMA to transfer data take a look at Labs 5 (to build the AXI BRAM hardware) and Lab 6 (using DMA to transfer data) of the Zynq Hardware Speedway workshop referenced above.

As to why all of your signals in the Vivado Analyzer are showing zeros, are you running some program on the Zynq to exercise your BRAM hardware and provide a trigger when you are attempting the trace?

You may need to spend a little time working through one of the Vivado Analyzer tutorials mentioned above or reading one of the Xilinx Users Guide listed below to be come familiar with how the debug tool works:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug908-vivado-programming-debugging.pdf

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug936-vivado-tutorial-programming-debugging.pdf

-Gary

Hi,


    actually I need normal write and read transfer between PS to PL. for tranfer data I was implemented hardware portion above mentioned. COE file initialize the data to contents of memory locations, just transfer that data to processor thus why I am using COE file.

Thanks & Regards
Ashwak ali S.

Hi,


    can you send the normal data transfer between PS to PL lab documents of Vivado 2011.1 version.


Thanks & Regards
Ashwak ali S.

If you are referring to the Avnet Speedway labs, they were designed using Vivado 2013.3 and we do not currently have a Vivado 2014.1 version available. You should be able to work through the labs with 2014.1 although there may be some differences. The other option is to experiment in Vivado 2013.3 until you are comfortable with your design and debugging and then build in the newer version of Vivado.

The ZedBoard Concepts Tools and Techniques tutorial has versions for Vivado 2013.4 and 2014.2 but not 2014.1.

-Gary

Hi,


    have any reference document about PS to PL communication on vivado 2013.4 version please send to me.


Thanks & Regards
Ashwak ali S.

I am not sure what documentation you are asking for that has not already been referenced above, except perhaps the Zynq TRM (Technical Reference Manual) ug58a5 which details the hardware specific details of the Zynq PS to PL interfaces: http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf

Otherwise the most pertinent documents on Zynq architecture, tutorials and debug references are listed above.

Could you be more specific in exactly what you are looking for that is not available on the Xilinx website?

-Gary